Camera Registers
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SWRU543–January 2019
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Parallel Camera Interface Module
Table 14-8. CC_CTRL Register Field Descriptions (continued)
Bit Field Type Reset Description
13 NOBT_SYNCHRO R/W 0h
Enables start at the beginning of the frame or not in NoBT
0h = Acquisition starts when vertical synchro is high
1h = Acquisition starts when vertical synchro goes from low to high
(beginning of the frame) (recommended)
12 BT_CORRECT R/W 1h
Enables the correct sync codes in BT mode.
0h = Correction is not enabled
1h = Correction is enabled
11 PAR_ORDERCAM R/W 0h
Enables swap between image-data in parallel mode.
0h = Swap is not enabled
1h = Swap is enabled
10 PAR_CLK_POL R/W 0h
Inverts the clock coming from the sensor in parallel mode.
0h = Clock not inverted - data sampled on rising edge
1h = Clock inverted - data sampled on falling edge
9 NOBT_HS_POL R/W 0h
Sets the polarity of the synchronization signals in NOBT parallel
mode.
0h = CAM_P_HS is active high
1h = CAM_P_HS is active low
8 NOBT_VS_POL R/W 0h
Sets the polarity of the synchronization signals in NOBT parallel
mode.
0h = CAM_P_VS is active high
1h = CAM_P_VS is active low
7-5 RESERVED R/W 0h
4 PORT_SELECT R/W 0h
Determines which OCP port can perform read access from internal
FIFO when DMA_EN bit is set to 1.
0h = OCP 2
1h = OCP 1
3-0 PAR_MODE R/W 1h
Sets the protocol mode of the camera core module in parallel mode
(when CCP_MODE = 0).
000h = Parallel NOBT 8-bit
001h = Parallel NOBT 10-bit
010h = Parallel NOBT 12-bit
011h = Reserved
100h = Parallel BT 8-bit
101h = Parallel BT 10-bit
110h = Reserved
111h = FIFO test mode.
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