DMA_MIS Register (offset = A0h) [reset = 0h]
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SWRU543–January 2019
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CC3235x Device Miscellaneous Registers
B.5 DMA_MIS Register (offset = A0h) [reset = 0h]
Register mask: FF0Fh
DMA_MIS is shown in Figure B-5 and described in Table B-6.
Figure B-5. DMA_MIS Register
31 30 29 28 27 26 25 24
RESERVED
R-X
23 22 21 20 19 18 17 16
RESERVED
R-X
15 14 13 12 11 10 9 8
ADCWR MCASPWR MCASPRD CAMEMPT CAMFULL
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
RESERVED APSPIWR APSPIRD SDIOMWR SDIOMRD
R-X R/W-0h R/W-0h R/W-0h R/W-0h
Table B-6. DMA_MIS Register Field Descriptions
Bit Field Type Reset Description
31-16 RESERVED R X
15-12 ADCWR R/W 0h
ADC_WR_DMA_DONE_INT_STS_MASKED
bit 15: ADC channel 6 DMA Done IRQ
bit 14: ADC channel 4 DMA Done IRQ
bit 13: ADC channel 2 DMA Done IRQ
bit 12: ADC channel 0 DMA Done IRQ
0h = Corresponding interrupt is inactive or masked by
DMA_DONE_INT mask.
1h = Corresponding interrupt is active and not masked. Read is non-
destructive.
11 MCASPWR R/W 0h
MCASP_WR_DMA_DONE_INT_STS_MASKED
0h = Corresponding interrupt is inactive or masked by
DMA_DONE_INT mask.
1h = Corresponding interrupt is active and not masked. Read is non-
destructive.
10 MCASPRD R/W 0h
MCASP_RD_DMA_DONE_INT_STS_MASKED
0h = Corresponding interrupt is inactive or masked by
DMA_DONE_INT mask.
1h = Corresponding interrupt is active and not masked. Read is non-
destructive.
9 CAMEMPT R/W 0h
CAM_FIFO_EMPTY_DMA_DONE_INT_STS_MASKED
0h = Corresponding interrupt is inactive or masked by
DMA_DONE_INT mask.
1h = Corresponding interrupt is active and not masked. Read is non-
destructive.
8 CAMFULL R/W 0h
CAM_THRESHHOLD_DMA_DONE_INT_STS_MASKED
0h = Corresponding interrupt is inactive or masked by
DMA_DONE_INT mask.
1h = Corresponding interrupt is active and not masked. Read is non-
destructive.
7-4 RESERVED R X
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