Texas Instruments CC3235 SimpleLink Series - Page 795

www.ti.com DMA_MIS Register (offset = A0h) [reset = 0h]
795
SWRU543–January 2019
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CC3235x Device Miscellaneous Registers
Table B-6. DMA_MIS Register Field Descriptions (continued)
Bit Field Type Reset Description
3 APSPIWR R/W 0h
APPS_SPI_WR_DMA_DONE_INT_STS_MASKED
0h = Corresponding interrupt is inactive or masked by
DMA_DONE_INT mask.
1h = Corresponding interrupt is active and not masked. Read is non-
destructive.
2 APSPIRD R/W 0h
APPS_SPI_RD_DMA_DONE_INT_STS_MASKED
0h = Corresponding interrupt is inactive or masked by
DMA_DONE_INT mask.
1h = Corresponding interrupt is active and not masked. Read is non-
destructive.
1 SDIOMWR R/W 0h
SDIOM_WR_DMA_DONE_INT_STS_MASKED
0h = Corresponding interrupt is inactive or masked by
DMA_DONE_INT mask.
1h = Corresponding interrupt is active and not masked. Read is non-
destructive.
0 SDIOMRD R/W 0h
SDIOM_RD_DMA_DONE_INT_STS_MASKED
0h = Corresponding interrupt is inactive or masked by
DMA_DONE_INT mask.
1h = Corresponding interrupt is active and not masked. Read is non-
destructive.