Texas Instruments CC3235 SimpleLink Series - Page 15

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15
SWRU543–January 2019
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List of Figures
4-16. DMA_REQMASKCLR Register ......................................................................................... 142
4-17. DMA_ENASET Register ................................................................................................. 143
4-18. DMA_ENACLR Register................................................................................................. 144
4-19. DMA_ALTSET Register.................................................................................................. 145
4-20. DMA_ALTCLR Register.................................................................................................. 146
4-21. DMA_PRIOSET Register ................................................................................................ 147
4-22. DMA_PRIOCLR Register................................................................................................ 148
4-23. DMA_ERRCLR Register................................................................................................. 149
4-24. DMA_CHASGN Register ................................................................................................ 150
4-25. DMA_CHMAP0 Register................................................................................................. 151
4-26. DMA_CHMAP1 Register................................................................................................. 152
4-27. DMA_CHMAP2 Register................................................................................................. 153
4-28. DMA_CHMAP3 Register................................................................................................. 154
4-29. DMA_PV Register ........................................................................................................ 155
5-1. Digital I/O Pads ........................................................................................................... 157
5-2. GPIODATA Write Example.............................................................................................. 158
5-3. GPIODATA Read Example.............................................................................................. 158
5-4. GPIODATA Register ..................................................................................................... 162
5-5. GPIODIR Register ........................................................................................................ 163
5-6. GPIOIS Register .......................................................................................................... 164
5-7. GPIOIBE Register ........................................................................................................ 165
5-8. GPIOIEV Register ........................................................................................................ 166
5-9. GPIOIM Register.......................................................................................................... 167
5-10. GPIORIS Register ........................................................................................................ 168
5-11. GPIOMIS Register........................................................................................................ 169
5-12. GPIOICR Register ........................................................................................................ 170
5-13. GPIO_TRIG_EN Register ............................................................................................... 171
6-1. UART Module Block Diagram........................................................................................... 175
6-2. UART Character Frame.................................................................................................. 176
6-3. UARTDR Register ........................................................................................................ 182
6-4. UARTRSR_UARTECR Register........................................................................................ 183
6-5. UARTFR Register ........................................................................................................ 185
6-6. UARTIBRD Register...................................................................................................... 187
6-7. UARTFBRD Register..................................................................................................... 188
6-8. UARTLCRH Register..................................................................................................... 189
6-9. UARTCTL Register....................................................................................................... 191
6-10. UARTIFLS Register ...................................................................................................... 193
6-11. UARTIM Register ......................................................................................................... 194
6-12. UARTRIS Register........................................................................................................ 196
6-13. UARTMIS Register ....................................................................................................... 198
6-14. UARTICR Register ....................................................................................................... 200
6-15. UARTDMACTL Register................................................................................................. 202
7-1. I2C Block Diagram........................................................................................................ 205
7-2. I2C Bus Configuration.................................................................................................... 206
7-3. START and STOP Conditions .......................................................................................... 207
7-4. Complete Data Transfer With a 7-Bit Address........................................................................ 207
7-5. R/S Bit in First Byte....................................................................................................... 207
7-6. Data Validity During Bit Transfer on the I2C Bus..................................................................... 208
7-7. Master Single TRANSMIT ............................................................................................... 214