Texas Instruments CC3235 SimpleLink Series - Page 16

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16
SWRU543–January 2019
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List of Figures
7-8. Master Single RECEIVE ................................................................................................. 215
7-9. Master TRANSMIT of Multiple Data Bytes ............................................................................ 216
7-10. Master RECEIVE of Multiple Data Bytes .............................................................................. 217
7-11. Master RECEIVE with Repeated START after Master TRANSMIT................................................ 218
7-12. Master TRANSMIT with Repeated START after Master RECEIVE................................................ 219
7-13. Slave Command Sequence ............................................................................................. 220
7-14. I2CMSA Register ......................................................................................................... 223
7-15. I2CMCS Register ......................................................................................................... 224
7-16. I2CMDR Register ......................................................................................................... 229
7-17. I2CMTPR Register........................................................................................................ 230
7-18. I2CMIMR Register ........................................................................................................ 231
7-19. I2CMRIS Register ........................................................................................................ 233
7-20. I2CMMIS Register ........................................................................................................ 235
7-21. I2CMICR Register ........................................................................................................ 237
7-22. I2CMCR Register ......................................................................................................... 239
7-23. I2CMCLKOCNT Register ................................................................................................ 240
7-24. I2CMBMON Register..................................................................................................... 241
7-25. I2CMBLEN Register...................................................................................................... 242
7-26. I2CMBCNT Register...................................................................................................... 243
7-27. I2CSOAR Register........................................................................................................ 244
7-28. I2CSCSR Register........................................................................................................ 245
7-29. I2CSDR Register.......................................................................................................... 247
7-30. I2CSIMR Register ........................................................................................................ 248
7-31. I2CSRIS Register......................................................................................................... 250
7-32. I2CSMIS Register......................................................................................................... 252
7-33. I2CSICR Register......................................................................................................... 254
7-34. I2CSOAR2 Register ...................................................................................................... 256
7-35. I2CSACKCTL Register................................................................................................... 257
7-36. I2CFIFODATA Register.................................................................................................. 258
7-37. I2CFIFOCTL Register.................................................................................................... 259
7-38. I2CFIFOSTATUS Register .............................................................................................. 261
7-39. I2CPP Register............................................................................................................ 262
7-40. I2CPC Register ........................................................................................................... 263
8-1. SPI Block Diagram........................................................................................................ 265
8-2. SPI Full-Duplex Transmission (Example).............................................................................. 267
8-3. Phase and Polarity Combinations ...................................................................................... 268
8-4. Full-Duplex Single Transfer Format With PHA = 0................................................................... 269
8-5. Full-Duplex Single Transfer Format With PHA = 1................................................................... 270
8-6. Contiguous Transfers With SPIEN Kept Active (Two Data Pins Interface Mode)................................ 272
8-7. Transmit/Receive Mode With No FIFO Used ......................................................................... 274
8-8. Transmit/Receive Mode With Only Receive FIFO Enabled......................................................... 274
8-9. Transmit/Receive Mode With Only Transmit FIFO Used............................................................ 275
8-10. Transmit/Receive Mode With Both FIFO Directions Used .......................................................... 275
8-11. Buffer Almost Full Level (AFL) .......................................................................................... 276
8-12. Buffer Almost Empty Level (AEL)....................................................................................... 276
8-13. 3-Pin Mode System Overview........................................................................................... 277
8-14. Flow Chart – Module Initialization ...................................................................................... 283
8-15. Flow Chart – Common Transfer Sequence ........................................................................... 284
8-16. Flow Chart – Transmit and Receive (Master and Slave)............................................................ 285