Texas Instruments CC3235 SimpleLink Series - Page 17

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17
SWRU543–January 2019
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List of Figures
8-17. Flow Chart – FIFO Mode Common Sequence (Master)............................................................. 286
8-18. Flow Chart – FIFO Mode Transmit and Receive With Word Count (Master)..................................... 288
8-19. Flow Chart – FIFO Mode Transmit and Receive without Word Count (Master).................................. 289
8-20. SPI_SYSCONFIG Register.............................................................................................. 291
8-21. SPI_SYSSTATUS Register.............................................................................................. 292
8-22. SPI_IRQSTATUS Register .............................................................................................. 293
8-23. SPI_IRQENABLE Register .............................................................................................. 295
8-24. SPI_MODULCTRL Register............................................................................................. 296
8-25. SPI_CHCONF Register .................................................................................................. 297
8-26. SPI_CHSTAT Register................................................................................................... 300
8-27. SPI_CHCTRL Register................................................................................................... 301
8-28. SPI_TX Register .......................................................................................................... 302
8-29. SPI_RX Register.......................................................................................................... 303
8-30. SPI_XFERLEVEL Register.............................................................................................. 304
9-1. GPTM Module Block Diagram .......................................................................................... 307
9-2. Input Edge-Count Mode Example, Counting Down .................................................................. 311
9-3. 16-Bit Input Edge-Time Mode Example................................................................................ 312
9-4. 16-Bit PWM Mode Example............................................................................................. 314
9-5. GPTMCFG Register...................................................................................................... 318
9-6. GPTMTAMR Register.................................................................................................... 319
9-7. GPTMTBMR Register.................................................................................................... 321
9-8. GPTMCTL Register....................................................................................................... 323
9-9. GPTMIMR Register....................................................................................................... 325
9-10. GPTMRIS Register ....................................................................................................... 327
9-11. GPTMMIS Register....................................................................................................... 329
9-12. GPTMICR Register....................................................................................................... 331
9-13. GPTMTAILR Register.................................................................................................... 333
9-14. GPTMTBILR Register.................................................................................................... 334
9-15. GPTMTAMATCHR Register............................................................................................. 335
9-16. GPTMTBMATCHR Register............................................................................................. 336
9-17. GPTMTAPR Register .................................................................................................... 337
9-18. GPTMTBPR Register .................................................................................................... 338
9-19. GPTMTAPMR Register .................................................................................................. 339
9-20. GPTMTBPMR Register .................................................................................................. 340
9-21. GPTMTAR Register ...................................................................................................... 341
9-22. GPTMTBR Register ...................................................................................................... 342
9-23. GPTMTAV Register ...................................................................................................... 343
9-24. GPTMTBV Register ...................................................................................................... 344
9-25. GPTMDMAEV Register .................................................................................................. 345
10-1. WDT Module Block Diagram ............................................................................................ 348
10-2. WDTLOAD Register...................................................................................................... 351
10-3. WDTVALUE Register .................................................................................................... 352
10-4. WDTCTL Register ........................................................................................................ 353
10-5. WDTICR Register......................................................................................................... 354
10-6. WDTRIS Register......................................................................................................... 355
10-7. WDTTEST Register ...................................................................................................... 356
10-8. WDTLOCK Register...................................................................................................... 357
10-9. Watchdog Flow Chart .................................................................................................... 359
10-10. System Watchdog Recovery Sequence ............................................................................... 360