Timer Registers
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SWRU543–January 2019
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General-Purpose Timers
Table 9-15. GPTMMIS Register Field Descriptions (continued)
Bit Field Type Reset Description
2 CAEMIS R X
GPTM Timer A Capture Mode Event Masked Interrupt. This bit is
cleared by writing 1 to the CAECINT bit in the GPTMICR register.
0h = A Capture A event interrupt has not occurred or is masked.
1h = An unmasked Capture A event interrupt has occurred.
1 CAMMIS R X
GPTM Timer A Capture Mode Match Masked Interrupt. This bit is
cleared by writing 1 to the CAMCINT bit in the GPTMICR register.
0h = A Capture A mode match interrupt has not occurred or is
masked.
1h = An unmasked Capture A match interrupt has occurred.
0 TATOMIS R X
GPTM Timer A Time-Out Masked Interrupt. This bit is cleared by
writing 1 to the TATOCINT bit in the GPTMICR register.
0h = A Timer A time-out interrupt has not occurred or is masked.
1h = An unmasked Timer A time-out interrupt has occurred.
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