Analog Devices SHARC ADSP-21368 - Page 162

SDRAM Controller
3-54 ADSP-21368 SHARC Processor Hardware Reference
In Table 3-23,
X16DE = 0, SDRAW[2:0] = id 100 (12 bits), and
SDCAW[1:0] = 11 (11 bits).
SDA10 IA[20] A[10]
A[10] IA[9] IA[19] A[9]
A[9] IA[8] IA[18] A[8]
A[8] IA[7] IA[17] A[7]
A[7] IA[6] IA[16] A[6]
A[6] IA[5] IA[15] A[5]
A[5] IA[4] IA[14] A[4]
A[4] IA[3] IA[13] A[3]
A[3] IA[2] IA[12] A[2]
A[2] IA[1] IA[11] A[1]
A[1] IA[0] IA[10] A[0]
A[0] Not USED for 32-bit SDRAMs
Table 3-23. 32-Bit Column, Row and Bank Address Mapping
(2K Words)
Pin Column Address Row Address Bank Address Pins of SDRAM
A[18] IA[24] BA[1]
A[17] IA[23] BA[0]
A[13] A[12]
A[12] IA[10] IA[22] A[11]
SDA10 IA[21] A[10]
A[10] IA[9] IA[20] A[9]
Table 3-22. 32-Bit Column, Row, and Bank Address Mapping
(1K Words) (Cont’d)
Pin Column Address Row Address Bank Address Pins of SDRAM