Renesas RX Series User Manual

R01UH0823EJ0100 Rev.1.00 Page 1026 of 1823
Jul 31, 2019
RX23W Group 33. Serial Communications Interface (SCIg, SCIh)
Figure 33.10 Example of Operation for Serial Transmission in Asynchronous Mode (1)
(with 8-Bit Data, Parity, 1 Stop Bit, CTS Function Not Used, at the Beginning of Transmission)
Figure 33.11 Example of Operation for Serial Transmission in Asynchronous Mode (2)
(with 8-Bit Data, Parity, 1 Stop Bit, CTS Function Used, at the Beginning of Transmission)
TXI interrupt flag
(IRn in ICU
*1
)
1 frame
Data
Parity bit Stop bitStart bit
TXI interrupt request
generated
TXI interrupt
request generated
Data written to TDR in
TXI interrupt handling
routine
SSR.TEND flag
0D0D1 D7
0/1D7
0/1 1
0D0
1
D1
Data written to TDR in
TXI interrupt handling
routine
SCR.TE bit
0
Data written to TDR in
TXI interrupt handling
routine
Note 1. Refer to section 15, Interrupt Controller (ICUb) for details on the corresponding interrupt vector number.
TXI interrupt flag
(IRn in ICU
*1
)
1 frame
Data
Parity bit Stop bitStart bit
Idle state
(mark state)
TXI interrupt request
generated
TXI interrupt request
generated
Data written to TDR
in TXI interrupt
handling routine
SSR.TEND flag
0D0D1 D7
0/1D7
0/1 1
0D0
1
D1
Data written to TDR in TXI
interrupt handling routine
SCR.TE bit
CTSn# pin
0
Data written to TDR in TXI
interrupt handling routine
Note 1. Refer to section 15, Interrupt Controller (ICUb) for details on the corresponding interrupt vector number.

Renesas RX Series Specifications

General

Core	RXv1, RXv2, RXv3
Flash Memory	Up to 8 MB
RAM	Up to 1 MB
Operating Voltage	1.62V to 5.5V
Operating Temperature	-40°C to +85°C or +105°C
Package	BGA, LQFP
ADC Resolution	12-bit
DAC Resolution	12-bit
Communication Interfaces	SCI, SPI, I2C, USB, Ethernet, CAN
Architecture	32-bit
Security Features	Memory Protection Unit (MPU)