Renesas RX Series User Manual

R01UH0823EJ0100 Rev.1.00 Page 1032 of 1823
Jul 31, 2019
RX23W Group 33. Serial Communications Interface (SCIg, SCIh)
Figure 33.17 Example Flowchart of Serial Reception in Asynchronous Mode (2)
End
Error processing
Parity error processing
Yes
No
Set the SSR.ORER, PER,
and FER flags to 0
No
Yes
No
Yes
Framing error processing
No
Yes
Overrun error processing
SSR.ORER flag = 1
SSR.FER flag = 1
Break?
SSR.PER flag = 1
Set RE bit in SCR to 0
[ 3 ]
[ 7 ] [ 7 ] Clearing the error flag:
Write 0 to the error flag.
[ 6 ]
[ 6 ] Processing in response to an overrun error:
Read the RDR. In combination with step [ 7 ], this
will make correct reception of the next frame possible.
Read the SSR.ORER, PER, and FER flags.
[ 8 ] [ 8 ] Confirming that the error flag is cleared:
Read the error flag to confirm that its value is 0.
Note: The RDR register becomes the RDRL register
when 9-bit data length is selected. Reading the
RDRH register is not necessary.

Renesas RX Series Specifications

General

Core	RXv1, RXv2, RXv3
Flash Memory	Up to 8 MB
RAM	Up to 1 MB
Operating Voltage	1.62V to 5.5V
Operating Temperature	-40°C to +85°C or +105°C
Package	BGA, LQFP
ADC Resolution	12-bit
DAC Resolution	12-bit
Communication Interfaces	SCI, SPI, I2C, USB, Ethernet, CAN
Architecture	32-bit
Security Features	Memory Protection Unit (MPU)