Renesas RX Series User Manual

R01UH0823EJ0100 Rev.1.00 Page 1031 of 1823
Jul 31, 2019
RX23W Group 33. Serial Communications Interface (SCIg, SCIh)
Figure 33.16 Example Flowchart of Serial Reception in Asynchronous Mode (1)
Yes
End
No
Initialization
Start data reception
No
Yes
Set bits RIE and RE in SCR to 0
Read ORER, PER, and FER flags in SSR
Error processing
(Continued to next page)
Read receive data in RDR
*1
No
Yes
RXI interrupt
All data received?
[ 1 ]
[ 2 ]
[ 3 ]
[ 4 ]
[ 5 ]
SSR.ORER flag = 1,
SSR.PER flag = 1, or
SSR.FER flag = 1
Note: The RDR register becomes the RDRH and RDRL registers
when 9-bit data length is selected. Read data in the order
from RDRH to RDRL.
[ 1 ] SCI initialization:
Set data reception.
[ 2 ] [ 3 ] Receive error processing and break detection:
If a receive error occurs, an ERI interrupt is
generated. An error is identified by reading the
ORER, PER, and FER flags in SSR. After
performing the appropriate error processing, be
sure to set the ORER, PER, and FER flags to 0.
Reception cannot be resumed if any of these
flags is set to 1. In the case of a framing error, a
break can be detected by reading the value of
the input port corresponding to the RXDn pin.
[ 4 ] Read the receive data in RDR once in the RXI
interrupt handling routine.
[ 5 ] Serial reception continuation procedure:
To continue serial reception, before the stop bit
of the current frame is received, read data from
RDR in the RXI interrupt handling routine.
The RDR data can also be read by activating
the DMAC or DTC.

Renesas RX Series Specifications

General

Core	RXv1, RXv2, RXv3
Flash Memory	Up to 8 MB
RAM	Up to 1 MB
Operating Voltage	1.62V to 5.5V
Operating Temperature	-40°C to +85°C or +105°C
Package	BGA, LQFP
ADC Resolution	12-bit
DAC Resolution	12-bit
Communication Interfaces	SCI, SPI, I2C, USB, Ethernet, CAN
Architecture	32-bit
Security Features	Memory Protection Unit (MPU)