R01UH0823EJ0100 Rev.1.00 Page 1037 of 1823
Jul 31, 2019
RX23W Group 33. Serial Communications Interface (SCIg, SCIh)
Figure 33.22 Example of Multi-Processor Serial Reception Flowchart (2)
End
Error processing
Yes
No
No
Yes
No
Yes
Framing error processing
Overrun error processing
SSR.ORER flag = 1
SSR.FER flag = 1
Break?
Set RE bit in SCR to 0
[ 5 ]
Set the SSR.ORER, PER,
and FER flags to 0.
[ 7 ]
[ 7 ] Clearing the error flag:
Write 0 to the error flag.
[ 6 ]
[ 6 ] Processing in response to an overrun error:
Read the RDR. In combination with step [ 7 ],
this will make correct reception of the next frame
possible.
Read the SSR.ORER, PER, and FER flags.
[ 8 ]
[ 8 ] Confirming that the error flag is cleared:
Read the error flag to confirm that its value is 0.
Note: The RDR register becomes the RDRH and RDRL
registers when 9-bit data length is selected. Read
data in the order from RDRH to RDRL.
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