R01UH0823EJ0100 Rev.1.00 Page 1057 of 1823
Jul 31, 2019
RX23W Group 33. Serial Communications Interface (SCIg, SCIh)
When transmitting/receiving data using the DTC or DMAC, be sure to make settings to enable the DTC or DMAC
before making SCI settings.
For DTC or DMAC settings, refer to
section 19, Data Transfer Controller (DTCa), section 18, DMA Controller
(DMACA)
.
Note that the SSR.TEND flag is set in different timings depending on the GM bit setting in the SMR register.
Figure
33.42
shows the TEND flag generation timing.
Figure 33.42 SSR.TEND Flag Generation Timing during Transmission
Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp
I/O data
12.5 etu (11.5 etu in block transfer mode)
SSR.TEND flag
(TXI interrupt)
11.0 etu
DE
Guard
time
When GM bit in SMR = 0
Ds: Start bit
D0 to D7: Data bits
Dp: Parity bit
DE: Error signal
When GM bit in SMR = 1
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