R01UH0823EJ0100 Rev.1.00 Page 1124 of 1823
Jul 31, 2019
RX23W Group 35. I
2
C-bus Interface (RIICa)
TMOH Bit (Timeout H Count Control)
This bit is used to enable or disable the internal counter of the timeout function to count up while the SCL0 line is held
high when the timeout function is enabled (ICFER.TMOE bit is 1).
SDDL[2:0] Bits (SDA Output Delay Counter)
The SDA output can be delayed by the SDDL[2:0] setting. This counter works with the clock source selected by the
DLCS bit. The setting of this function can be used for all types of SDA output, including the transmission of the
acknowledge bit.
Set the SDA output delay time to meet the I
2
C-bus specification (within the data enable time/acknowledge enable
time
*
1
) or the SMBus specification (within the data hold time: 300 ns or more, and SCL-clock low-level period - the data
setup time: 250 ns). Note that, if a value outside the specification is set, communication with communication devices
may malfunction or it may seemingly become a start condition or stop condition depending on the bus state.
For details on this function, refer to
section 35.5, SDA Output Delay Function.
Note 1. Data enable time/acknowledge enable time
3,450 ns (up to 100 kbps: Standard-mode (Sm))
900 ns (up to 400 kbps: Fast-mode (Fm))
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