R01UH0823EJ0100 Rev.1.00 Page 1154 of 1823
Jul 31, 2019
RX23W Group 35. I
2
C-bus Interface (RIICa)
Figure 35.12 Master Receive Operation Timing (1) (7-Bit Address Format, When RDRFS bit is 0)
Figure 35.13 Master Receive Operation Timing (2) (10-Bit Address Format, When RDRFS bit is 0)
Read ICDRR register
(Dummy read)
Read ICDRR register
(DATA 1)
Write data to ICDRT register
(7-bit address + R)
Write 1
to ST bit
X(ACK/NACK)
0(ACK)
XXXX (Initial value/last data for reception) XXXX (Initial value/last data for reception)
7-bit address + R
Transmit data (7-bit address + R)
7-bit slave address
Automatic low hold
(to prevent wrong transmission)
TDRE
MST
TRS
BBSY
TEND
S 9
ST
START
ICDRT
ICDRS
DATA 1 DATA 2
1
b7
R
2
b6
3
b5
4
b4
5
b3
6
b2
7
b1
2
b6
4
b4
5
b3
6
b2
7
b1
3
b5
8
b0
1
b7
2
b6
4
b4
3
b5
DATA 1 DATA 2
1
b7
RDRF
ICDRR DATA 1
98
b0
Master transmit mode Master receive mode
ACKBT
ACKBR
[3] [4] [5][2]
0 (ACK) 0 (ACK)
ACK
Receive data (7-bit address + R)
7-bit address + R
ACK
Receive data (DATA 1)
Write 1
to ST bit
Write data to ICDRT
register
(11110b + 2 bits + R)
0(ACK)
XXXX (Initial value/last data for reception)
XXXX (Initial value/last data for reception )
Upper 10 bits + R
Upper 10 bits + R
Master transmit mode Master receive mode
Automatic low hold (to prevent wrong transmission)
Read ICDRR register
(Dummy read)
Upper 10 bits + W
TDRE
MST
TRS
BBSY
TEND
S
ST
START
ICDRT
ICDRS
DATA 1
W
7
b1
1
b7
2
b6
4
b4
3
b5
DATA 1
RDRF
ICDRR
Upper 10-bit addresses (11110b + 2 bits) R
98
b0
2
b6
3
b5
4
b4
5
b3
1
b7
6
b2
Sr1
to
8 998
b0
1
to
7
b7 b1
Lower 10 bitsUpper 10 bits
RS
ACKBT
ACKBR
[3] [4][2]
Upper 10 bits + W
Lower 10 bits
0 (ACK) 0 (ACK)0(ACK)
Write 1
to RS bit
Clear
START flag
Write data to
ICDRT register
(lower 8 bits)
Write data to ICDRT
register
(11110b + 2 bits + W)
Transmit data (lower 10 bits)Transmit data (upper 10 bits + W)
Transmit data (upper 10 bits + R)
Transmit data (upper 10 bits + R)
ACKACKACK
X (ACK/NACK)
Lower 10 bits
b7 b0
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