R01UH0823EJ0100 Rev.1.00 Page 1305 of 1823
Jul 31, 2019
RX23W Group 37. Serial Sound Interface (SSI)
Note 1. While this module is muted, low is transmitted regardless of the value of serial data, but data transmission is not stopped. Since
the number of data in the transmit FIFO decreases, write dummy data to the SSIFTDR register to prevent the generation of a
transmit underflow. When the MUEN bit is set to 1, the SSITXD0 pin immediately becomes low without synchronizing SSIWS0
pin.
Note 2. Set the SCKD and SWSD bits to the same value. Other settings are prohibited.
Note 3. Rewriting is allowed only in the idle state.
b12 SWSP Word Select Polarity 0: SSIWS0 is low for the 1st system word, high for the 2nd
system word.
1: SSIWS0 is high for the 1st system word, low for the 2nd
system word.
R/W
b13 SCKP Serial Bit Clock Polarity*
3
0: SSIWS0 and SSITXD0 change at the SSISCK0 falling edge
(SSIWS0 and SSIRXD0 are sampled at the SSISCK0 rising
edge).
1: SSIWS0 and SSITXD0 change at the SSISCK0 rising edge
(SSIWS0 and SSITXD0 are sampled at the SSISCK0 falling
edge).
R/W
b14 SWSD Word Select Direction*
2,
*
3
0: SSIWS0 pin is input (slave mode).
1: SSIWS0 pin is output (master mode).
R/W
b15 SCKD Serial Bit Clock Direction*
2,
*
3
0: SSISCK0 pin is input (slave mode).
1: SSISCK0 pin is output (master mode).
R/W
b18 to b16 SWL[2:0] System Word Length*
3
Set the system word length to the bit clock frequency/2 fs.
b18 b16
0 0 0: 8 bits (serial bit clock frequency = 16 fs)
0 0 1: 6 bits (serial bit clock frequency = 32 fs)
0 1 0: 24 bits (serial bit clock frequency = 48 fs)
0 1 1: 32 bits (serial bit clock frequency = 64 fs)
Settings other than above are prohibited.
R/W
b21 to b19 DWL[2:0] Data Word Length*
3
b21 b19
000:8 bits
0 0 1: 16 bits
0 1 0: 18 bits
0 1 1: 20 bits
1 0 0: 22 bits
1 0 1: 24 bits
Settings other than above are prohibited.
R/W
b23, b22 CHNL[1:0] Channels*
3
b23 b22
0 0: One channel
Settings other than above are prohibited.
R/W
b24 — Reserved This bit is read as 0. The write value should be 0. R/W
b25 IIEN Idle Interrupt Enable 0: Disables an idle interrupt.
1: Enables an idle interrupt.
R/W
b26 ROIEN Receive Overflow Interrupt
Enable
0: Disables a receive overflow interrupt.
1: Enables a receive overflow interrupt.
R/W
b27 RUIEN Receive Underflow Interrupt
Enable
0: Disables a receive underflow interrupt.
1: Enables a receive underflow interrupt.
R/W
b28 TOIEN Transmit Overflow Interrupt
Enable
0: Disables a transmit overflow interrupt.
1: Enables a transmit overflow interrupt.
R/W
b29 TUIEN Transmit Underflow Interrupt
Enable
0: Disables a transmit underflow interrupt.
1: Enables a transmit underflow interrupt.
R/W
b30 CKS Audio Clock Select*
3
0: AUDIO_MCLK input
1: Main clock
R/W
b31 — Reserved This bit is read as 0. The write value should be 0. R/W
Bit Symbol Bit Name Description R/W
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