R01UH0823EJ0100 Rev.1.00 Page 137 of 1823
Jul 31, 2019
RX23W Group 6. Resets
The internal state and pins are initialized by a reset.
Table 6.2 lists the reset targets to be initialized.
: Targets to be initialized, —: No change occurs.
Note 1. Initialized at a power-on.
Note 2. Some control bits (RCR1.CIE, RCR1.RTCOS, RCR2.RTCOE, ADJ30, and RESET) are initialized by all types of reset. For
details on the target bits, refer to section 28, Realtime Clock (RTCe).
When a reset is canceled, the reset exception handling starts. For the reset exception handling, see section 14,
Exception Handling
.
Table 6.3 lists the pin related to the reset.
Table 6.2 Targets Initialized by Each Reset Source
Target to be Initialized
Reset Source
RES# Pin Reset
Power-On
Reset
Voltage
Monitoring 0
Reset
Independent
Watchdog
Timer Reset
Watchdog
Timer Reset
Voltage
Monitoring 1
Reset Software Reset
The power-on reset detect flag
(RSTSR0.PORF)
——————
Register related to the cold start/warm start
determination flag
(RSTSR1.CWSF)
—*
1
—————
Voltage monitoring 0 reset detect flag
(RSTSR0.LVD0RF)
—————
Registers related to the battery backup
function
(VBATTCR, VBATTSR, VBTLVDICR)
—————
The independent watchdog timer reset
detect flag
(RSTSR2.IWDTRF)
————
Registers related to the independent
watchdog timer
(IWDTRR, IWDTCR, IWDTSR, IWDTRCR,
IWDTCSTPR, ILOCOCR)
————
The watchdog timer reset detect flag
(RSTSR2.WDTRF)
———
Registers related to the watchdog timer
(WDTRR, WDTCR, WDTSR, WDTRCR)
———
The voltage monitoring 1 reset detect flag
(RSTSR0.LVD1RF)
——
Registers related to voltage monitor
function 1
(LVD1CR0, LVCMPCR.LVD1E,
LVDLVLR.LVD1LVL[3:0])
——
(LVD1CR1, LVD1SR)
——
The software reset detect flag
(RSTSR2.SWRF)
—
Register related to the realtime clock*
2
— ——————
Registers other than the above, CPU, and
internal state
Table 6.3 Pin Related to Reset
Pin Name I/O Function
RES# Input Reset pin
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