15.4.7 Digital Filter ............................................................................................................................. 301
15.4.8 External Pin Interrupts .............................................................................................................. 301
15.5 Non-maskable Interrupt Operation .................................................................................................... 302
15.6 Return from Power-Down States ....................................................................................................... 303
15.6.1 Return from Sleep Mode or Deep Sleep Mode ........................................................................ 303
15.6.2 Return from Software Standby Mode ....................................................................................... 303
15.7 Usage Note ........................................................................................................................................ 304
15.7.1 Note on WAIT Instruction Used with Non-Maskable Interrupt ............................................... 304
16. Buses ........................................................................................................................................... 305
16.1 Overview ........................................................................................................................................... 305
16.2 Description of Buses .......................................................................................................................... 307
16.2.1 CPU Buses ................................................................................................................................ 307
16.2.2 Memory Buses .......................................................................................................................... 307
16.2.3 Internal Main Buses .................................................................................................................. 307
16.2.4 Internal Peripheral Buses .......................................................................................................... 308
16.2.5 Write Buffer Function (Internal Peripheral Bus) ...................................................................... 309
16.2.6 Parallel Operation ..................................................................................................................... 310
16.3 Register Descriptions ......................................................................................................................... 311
16.3.1 Bus Error Status Clear Register (BERCLR) ............................................................................. 311
16.3.2 Bus Error Monitoring Enable Register (BEREN) .................................................................... 311
16.3.3 Bus Error Status Register 1 (BERSR1) .................................................................................... 312
16.3.4 Bus Error Status Register 2 (BERSR2) .................................................................................... 312
16.3.5 Bus Priority Control Register (BUSPRI) .................................................................................. 313
16.4 Bus Error Monitoring Section ........................................................................................................... 315
16.4.1 Types of Bus Error ................................................................................................................... 315
16.4.1.1 Illegal Address Access .................................................................................................... 315
16.4.1.2 Timeout ............................................................................................................................ 315
16.4.2 Operations When a Bus Error Occurs ...................................................................................... 316
16.4.3 Conditions Leading to Bus Errors ............................................................................................ 316
16.5 Interrupt ............................................................................................................................................. 317
16.5.1 Interrupt Source ........................................................................................................................ 317
17. Memory-Protection Unit (MPU) .................................................................................................
... 318
17.1 Overview ........................................................................................................................................... 318
17.1.1 Types of Access Control ........................................................................................................... 320
17.1.2 Regions for Access Control ...................................................................................................... 320
17.1.3 Background Region .................................................................................................................. 320
17.1.4 Overlap between Regions ......................................................................................................... 320
17.1.5 Instructions and Data that Span Regions .................................................................................. 320
17.2 Register Descriptions ......................................................................................................................... 321
17.2.1 Region-n Start Page Number Register (RSPAGEn) (n = 0 to 7) ............................................. 321
17.2.2 Region-n End Page Number Register (REPAGEn) (n = 0 to 7) .............................................. 322
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