Renesas RX Series

14.5.3 Access Exceptions .................................................................................................................... 265
14.5.4 Floating-Point Exception .......................................................................................................... 265
14.5.5 Reset ......................................................................................................................................... 265
14.5.6 Non-Maskable Interrupt ........................................................................................................... 266
14.5.7 Interrupt .................................................................................................................................... 266
14.5.8 Unconditional Trap ................................................................................................................... 266
14.6 Return from Exception Handling Routine ......................................................................................... 267
14.7 Priority of Exception Events .............................................................................................................. 267
15. Interrupt Controller (ICUb) ........................................................................................................... 268
15.1 Overview ........................................................................................................................................... 268
15.2 Register Descriptions ......................................................................................................................... 270
15.2.1 Interrupt Request Register n (IRn) (n = interrupt vector number) ........................................... 270
15.2.2 Interrupt Request Enable Register m (IERm) (m = 02h to 1Fh) .............................................. 271
15.2.3 Interrupt Source Priority Register n (IPRn) (n = interrupt vector number) .............................. 272
15.2.4 Fast Interrupt Set Register (FIR) .............................................................................................. 273
15.2.5 Software Interrupt Generation Register (SWINTR) ................................................................. 274
15.2.6 DTC Transfer Request Enable Register n (DTCERn)
(n = interrupt vector number) ................................................................................................... 275
15.2.7 DMAC Trigger Select Register m (DMRSRm) (m = DMAC channel number) ..................... 276
15.2.8 IRQ Control Register i (IRQCRi) (i = 0, 1, and 4 to 7) ............................................................ 277
15.2.9 IRQ Pin Digital Filter Enable Register 0 (IRQFLTE0) ............................................................ 278
15.2.10 IRQ Pin Digital Filter Setting Register 0 (IRQFLTC0) ........................................................... 279
15.2.11 Non-Maskable Interrupt Status Register (NMISR) .................................................................. 280
15.2.12 Non-Maskable Interrupt Enable Register (NMIER) ................................................................ 282
15.2.13 Non-Maskable Interrupt Status Clear Register (NMICLR) ..................................................... 284
15.2.14 NMI Pin Interrupt Control Register (NMICR) ......................................................................... 285
15.2.15 NMI Pin Digital Filter Enable Register (NMIFLTE) ............................................................... 285
15.2.16 NMI Pin Digital Filter Setting Register (NMIFLTC) .............................................................. 286
15.3 Vector Table ...................................................................................................................................... 287
15.3.1 Interrupt Vector Table .............................................................................................................. 287
15.3.2 Fast Interrupt Vector Table ....................................................................................................... 293
15.3.3 Non-maskable Interrupt Vector Area ....................................................................................... 293
15.4 Interrupt Operation ............................................................................................................................ 294
15.4.1 Detecting Interrupts .................................................................................................................. 294
15.4.1.1 Operation of Status Flags
for Edge-Detected Interrupts ................................................. 294
15.4.1.2 Operation of Status Flags for Level-Detected Interrupts ................................................ 296
15.4.2 Enabling and Disabling Interrupt Sources ................................................................................ 297
15.4.3 Selecting Interrupt Request Destinations ................................................................................. 298
15.4.4 Determining Priority ................................................................................................................. 300
15.4.5 Multiple Interrupts .................................................................................................................... 300
15.4.6 Fast Interrupt ............................................................................................................................. 300