Renesas RX Series

R01UH0823EJ0100 Rev.1.00 Page 1468 of 1823
Jul 31, 2019
RX23W Group 40. SD Host Interface (SDHIa)
Figure 40.22 shows an example of data being DMA transferred to the SDBUFR register after the CMD25 multi-block
write command is issued.
Figure 40.22 DMA Transfer After CMD25 is Issued
Clear the flag register
Set the SDCLKCR register
Did a response end
or error occur?
Clear the flag and check the response
Issue CMD25 (multi-block write command)
Error (communication error or timeout)
Did an access end
or error occur?
Clear the flag and check the response
Disable DMA transfer to the SDBUFR register
Error (communication error or timeout)
Enable DMA transfer to the SDBUFR register
SDDMAEN register
 0000 0002h
No
Response end
Access end
SDDMAEN register
 0000 0000h
No
Start
Set the DMAC or DTC
Set the DMAC or DTC
Error processing (clear the interrupt flags)
(setting to disable DMA transfer to the SDBUFR register)
End