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R01UH0823EJ0100 Rev.1.00 Page 173 of 1823

Jul 31, 2019

RX23W Group 9. Clock Generation Circuit

Note: Set the PRCR.PRC0 bit to 1 (write enabled) before rewriting this register.

Note 1. Do not set the frequency division ratio of ICLK = 1 when a clock of frequency higher than 32 MHz is selected by the

SCKCR3.CKSEL[2:0] bits and MEMWAIT.MEMWAIT = 0.

This register cannot be rewritten while the flash memory is being programmed or erased.

When an instruction for writing to SCKCR or SCKCR3 is to follow writing to the SCKCR register, do so in accord with

the procedure below.

1. Write to the SCKCR register.

2. Confirm that the value has actually been written to the SCKCR register.

3. Proceed to the next step.

PCKD[3:0] Bits (Peripheral Module Clock D (PCLKD) Select)

These bits select the frequency of peripheral module clock D (PCLKD).

PCKB[3:0] Bits (Peripheral Module Clock B (PCLKB) Select)

These bits select the frequency of peripheral module clock B (PCLKB).

PCKA[3:0] Bits (Peripheral Module Clock A (PCLKA) Select)

These bits select the frequency of peripheral module clock A (PCLKA).

ICK[3:0] Bits (System Clock (ICLK) Select)

These bits select the frequency of the system clock (ICLK).

FCK[3:0] Bits (FlashIF Clock (FCLK) Select)

These bits select the frequency of the FlashIF clock (FCLK).

b31 to b28 FCK[3:0] FlashIF Clock (FCLK)

Select

b31 b28

0 0 0 0: ×1

0 0 0 1: ×1/2

0 0 1 0: ×1/4

0 0 1 1: ×1/8

0 1 0 0: ×1/16

0 1 0 1: ×1/32

0 1 1 0: ×1/64

Settings other than above are prohibited.

R/W

Bit Symbol Bit Name Description R/W

Renesas RX Series User Manual

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