R01UH0823EJ0100 Rev.1.00 Page 222 of 1823
Jul 31, 2019
RX23W Group 11. Low Power Consumption
“Operating possible” means that operating or stopped can be controlled by the register setting.
“Stopped (Retained)” means that internal register values are retained and internal operations are suspended.
Note 1. “Interrupts” here indicates an external pin interrupt (the NMI, IRQ0, IRQ1, or IRQ4 to IRQ7) or any of peripheral interrupts (the
RTC alarm, RTC interval, IWDT, voltage monitoring, VBATT pin voltage drop detection, USB and ELC (LPT-dedicated interrupt)
interrupts).
Note 2. This does not include a RES# pin reset, power-on reset, voltage monitoring reset, or independent watchdog-timer reset. One of
these reset sources initiate transition to reset state.
Note 3. Operating or stopping is selected by setting the IWDT sleep mode count stop control bit (IWDTSLCSTP) in option function
select register 0 (OFS0) in IWDT auto-start mode. In any mode other than IWDT auto-start mode, operating or stopping is
selected by the setting of the sleep mode count stop control bit (SLCSTP) in the IWDT count stop control register
(IWDTCSTPR).
Note 4. The peripheral logic states are retained.
Note 5. During sleep mode, do not write to the system control related registers (indicated by ‘SYSTEM’ in the Module Symbol column in
Table 5.1, List of I/O Registers (Address Order).
Note 6. Stopped when the clock output source select bits (CKOCR.CKOSEL[2:0]) are set to a value other than 011b (sub-clock
oscillator).
Note 7. Using the digital filter function is prohibited. Operation for outputting the comparison result to the CMPOBn pin is possible.
Note 8. When the low-power timer clock source select bit in the low-power timer control register 1 (LPTCR1.LPCNTCKSEL) is 1
(selecting IWDT-dedicated on-chip oscillator), operating or stopping can be selected as described in Note 3. When the value of
the bit is 0 (selecting the sub-clock oscillator), only operating is possible.
Table 11.2 Operating Conditions of Each Power Consumption Mode
Entering and Exiting Low
Power Consumption Modes
and Operating States Sleep Mode Deep Sleep Mode Software Standby Mode
Entry trigger Control register + instruction Control register + instruction Control register + instruction
Exit trigger Interrupt Interrupt Interrupt*
1
After exiting from each mode, CPU
begins from*
2
Interrupt handling Interrupt handling Interrupt handling
Main clock oscillator Operating possible Operating possible Stopped
Sub-clock oscillator Operating possible Operating possible Operating possible
High-speed on-chip oscillator Operating possible Operating possible Stopped
Low-speed on-chip oscillator Operating possible Operating possible Stopped
IWDT-dedicated on-chip oscillator Operating possible*
3
Operating possible*
3
Operating possible*
3
PLL Operating possible Operating possible Stopped
USB-dedicated PLL Operating possible Operating possible Stopped
CPU Stopped (Retained) Stopped (Retained) Stopped (Retained)
RAM (0000 0000h to 0000 FFFFh) Operating possible (Retained) Stopped (Retained) Stopped (Retained)
DMAC Operating possible*
5
Stopped (Retained) Stopped (Retained)
DTC Operating possible*
5
Stopped (Retained) Stopped (Retained)
Flash memory Operating Stopped (Retained) Stopped (Retained)
Watchdog timer (WDT) Stopped (Retained) Stopped (Retained) Stopped (Retained)
Independent watchdog timer (IWDT) Operating possible*
3
Operating possible*
3
Operating possible*
3
Realtime clock (RTC) Operating possible Operating possible Operating possible
Low power timer (LPT) Operating possible*
8
Operating possible*
8
Operating possible*
8
Voltage detection circuit (LVD) Operating possible Operating possible Operating possible
Power-on reset circuit Operating Operating Operating
Peripheral modules Operating possible Operating possible Stopped (Retained)*
4
I/O ports Operating Operating Retained
RTCOUT Operating possible Operating possible Operating possible
CLKOUT Operating possible Operating possible Operating possible*
6
Comparator B Operating possible Operating possible Operating possible*
7
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