Renesas RX Series User Manual

R01UH0823EJ0100 Rev.1.00 Page 362 of 1823
Jul 31, 2019
RX23W Group 18. DMA Controller (DMACA)
When an interrupt by an extended repeat area overflow is used in block transfer mode, the following should be taken into
consideration.
When a transfer is stopped by an interrupt by an extended repeat area overflow, the address register must be set so that
the block size is a power of 2 or the block size boundary is aligned with the extended repeat area boundary. When an
overflow on the extended repeat area occurs during a transfer of one block, the interrupt by the overflow is suspended
until transfer of the block is completed, and the transfer overruns.
Figure 18.6 shows an example when the extended repeat area function is used in block transfer mode.
Figure 18.6 Example of Extended Repeat Area Function in Block Transfer Mode
Example:
Eight bytes are specified as an extended repeat area by the lower three bits of DMACm.DMSAR (SARA[4:0] bits in
DMACm.DMAMD = 00011b),
block transfer mode with block size 5 is set (DMACm.DMCRA = 00050005h), and
transfer source address is not specified as a block area.
Data size is eight bits (SZ[1:0] bits in DMACm.DMTMD = 00b).
Memory area
Repeated
00013FFEh
00013FFFh
00014000h
00014001h
00014002h
00014003h
00014004h
00014005h
00014006h
00014007h
00014008h
00014009h
00014000h
00014001h
00014002h
00014003h
00014004h
00014005h
00014006h
00014007h
Block transfer
continued
DMSAR value
range
00014000h
00014001h
00014002h
00014003h
00014004h
00014005h
00014006h
00014007h
00014000h
00014001h
First block transfer
Second block
transfer
Interrupt request
generated

Renesas RX Series Specifications

General

Core	RXv1, RXv2, RXv3
Flash Memory	Up to 8 MB
RAM	Up to 1 MB
Operating Voltage	1.62V to 5.5V
Operating Temperature	-40°C to +85°C or +105°C
Package	BGA, LQFP
ADC Resolution	12-bit
DAC Resolution	12-bit
Communication Interfaces	SCI, SPI, I2C, USB, Ethernet, CAN
Architecture	32-bit
Security Features	Memory Protection Unit (MPU)