36.7 Interrupt ........................................................................................................................................... 1278
36.8 RAM Window ................................................................................................................................. 1281
36.9 Initial Settings .................................................................................................................................. 1282
36.9.1 Clock Setting .......................................................................................................................... 1283
36.9.2 Bit Timing Setting .................................................................................................................. 1283
36.9.3 Communication Speed Setting ............................................................................................... 1284
36.9.4 Receive Rule Setting .............................................................................................................. 1285
36.9.5 Buffer Setting ......................................................................................................................... 1286
36.10 Reception Procedure ........................................................................................................................ 1287
36.10.1 Receive Buffer Reading Procedure ........................................................................................ 1287
36.10.2 FIFO Buffer Reading Procedure ............................................................................................. 1289
36.11 Transmission Procedure .................................................................................................................. 1291
36.11.1 Procedure for Transmission from Transmit Buffers ............................................................... 1291
36.11.2 Procedure for Transmission from Transmit/Receive FIFO Buffers ....................................... 1294
36.11.3 Transmit History Buffer Reading Procedure .......................................................................... 1297
36.12 Test Settings .................................................................................................................................... 1298
36.12.1 Self-Test Mode Setting Procedure .......................................................................................... 1298
36.12.2 Protection Unlock Procedure .................................................................................................. 1299
36.12.3 RAM Test Setting Procedure .................................................................................................. 1300
36.13 Notes on the CAN Module .............................................................................................................. 1301
37. Serial Sound Interface (SSI) ...................................................................................................... 1302
37.1 Overview .........................................................................................................................................
1302
37.2 Register Descriptions ....................................................................................................................... 1304
37.2.1 Control Register (SSICR) ....................................................................................................... 1304
37.2.2 Status Register (SSISR) .......................................................................................................... 1308
37.2.3 FIFO Control Register (SSIFCR) ........................................................................................... 1310
37.2.4 FIFO Status Register (SSIFSR) .............................................................................................. 1312
37.2.5 Transmit FIFO Data Register (SSIFTDR) .............................................................................. 1314
37.2.6 Receive FIFO Data Register (SSIFRDR) ............................................................................... 1314
37.2.7 TDM Mode Register (SSITDMR) .......................................................................................... 1315
37.3 Operation ......................................................................................................................................... 1316
37.3.1 Bus Format ............................................................................................................................. 1316
37.3.2 Non-Compressed Mode .......................................................................................................... 1316
37.3.3 WS Continue Mode ................................................................................................................ 1322
37.3.4 Operating States ...................................................................................................................... 1323
37.3.5 Transmit Operation ................................................................................................................. 1324
37.3.6 Receive Operation .................................................................................................................. 1327
37.3.7 Serial Bit Clock Control ......................................................................................................... 1329
37.4 Interrupt Sources .............................................................................................................................. 1329
37.5 Usage Notes ..................................................................................................................................... 1330
37.5.1 Setting the Module Stop Function .......................................................................................... 1330
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