Renesas RX Series

37.5.2 Notes on Changing Transmission Modes ............................................................................... 1330
37.5.3 Limits on WS Continue Mode ................................................................................................ 1330
38. Serial Peripheral Interface (RSPIa) ............................................................................................ 1331
38.1 Overview ......................................................................................................................................... 1331
38.2 Register Descriptions ....................................................................................................................... 1335
38.2.1 RSPI Control Register (SPCR) ............................................................................................... 1335
38.2.2 RSPI Slave Select Polarity Register (SSLP) .......................................................................... 1337
38.2.3 RSPI Pin Control Register (SPPCR) ...................................................................................... 1338
38.2.4 RSPI Status Register (SPSR) .................................................................................................. 1339
38.2.5 RSPI Data Register (SPDR) ................................................................................................... 1342
38.2.6 RSPI Sequence Control Register (SPSCR) ............................................................................ 1345
38.2.7 RSPI Sequence Status Register (SPSSR) ............................................................................... 1346
38.2.8 RSPI Bit Rate Register (SPBR) .............................................................................................. 1347
38.2.9 RSPI Data Control Register (SPDCR) ................................................................................... 1348
38.2.10 RSPI Clock Delay Register (SPCKD) .................................................................................... 1350
38.2.11 RSPI Slave Select Negation Delay Register (SSLND) .......................................................... 1351
38.2.12 RSPI Next-Access Delay Register (SPND) ............................................................................ 1352
38.2.13 RSPI Control Register 2 (SPCR2) .......................................................................................... 1353
38.2.14 RSPI Command Register m (SPCMDm) (m = 0 to 7) ........................................................... 1355
38.3 Operation ......................................................................................................................................... 1358
38.3.1 Overview of RSPI Operations ................................................................................................ 1358
38.3.2 Controlling RSPI Pins ............................................................................................................ 1359
38.3.3 RSPI System Configuration Examples ................................................................................... 1360
38.3.3.1 Single Master/Single Slave (with This MCU Acting as Master) ..................................
1360
38.3.3.2 Single Master/Single Slave (with This MCU Acting as Slave) .................................... 1361
38.3.3.3 Single Master/Multi-Slave (with This MCU Acting as Master) ................................... 1362
38.3.3.4 Single Master/Multi-Slave (with This MCU Acting as Slave) ..................................... 1363
38.3.3.5 Multi-Master/Multi-Slave (with This MCU Acting as Master) .................................... 1364
38.3.3.6 Master (Clock Synchronous Operation)/Slave (Clock Synchronous Operation)
(with This MCU Acting as Master) ............................................................................... 1365
38.3.3.7 Master (Clock Synchronous Operation)/Slave (Clock Synchronous Operation)
(with This MCU Acting as Slave) ................................................................................. 1365
38.3.4 Data Format ............................................................................................................................ 1366
38.3.4.1 When Parity is Disabled (SPCR2.SPPE = 0) ................................................................ 1367
38.3.4.2 When Parity is Enabled (SPCR2.SPPE = 1) ................................................................. 1371
38.3.5 Transfer Format ...................................................................................................................... 1375
38.3.5.1 CPHA = 0 ...................................................................................................................... 1375
38.3.5.2 CPHA = 1 ...................................................................................................................... 1376
38.3.6 Communications Operating Mode .......................................................................................... 1377
38.3.6.1 Full-Duplex Synchronous Serial Communications (SPCR.TXMD = 0) ....................... 1377
38.3.6.2 Transmit Operations Only (SPCR.TXMD = 1) ............................................................. 1378