38.3.7 Transmit Buffer Empty/Receive Buffer Full Interrupts ......................................................... 1379
38.3.8 Error Detection ....................................................................................................................... 1381
38.3.8.1 Overrun Error ................................................................................................................ 1382
38.3.8.2 Parity Error .................................................................................................................... 1384
38.3.8.3 Mode Fault Error ........................................................................................................... 1385
38.3.9 Initializing RSPI ..................................................................................................................... 1386
38.3.9.1 Initialization by Clearing the SPE Bit ........................................................................... 1386
38.3.9.2 System Reset ................................................................................................................. 1386
38.3.10 SPI Operation ......................................................................................................................... 1387
38.3.10.1 Master Mode Operation ................................................................................................. 1387
38.3.10.2 Slave Mode Operation ................................................................................................... 1397
38.3.11 Clock Synchronous Operation ................................................................................................ 1401
38.3.11.1 Master Mode Operation ................................................................................................. 1401
38.3.11.2 Slave Mode Operation ................................................................................................... 1405
38.3.12 Loopback Mode ...................................................................................................................... 1407
38.3.13 Self-Diagnosis of Parity Bit Function .................................................................................... 1408
38.3.14 Interrupt Sources ..................................................................................................................... 1409
38.4 Link Operation by Event Linking .................................................................................................... 1410
38.4.1 Receive Buffer Full Event Output .......................................................................................... 1410
38.4.2 Transmit Buffer Empty Event Output .................................................................................... 1410
38.4.3 Mode Fault, Overrun, or Parity Error Event Output ............................................................... 1410
38.4.4 RSPI Idle Event Output .......................................................................................................... 1411
38.4.5 Transmission-Completed Event Output ................................................................................. 1411
38.5 Usage Notes ..................................................................................................................................... 1412
38.5.1 Setting Module Stop Function ................................................................................................ 1412
38.5.2 Note on Low Power Consumption Functions ......................................................................... 1412
38.5.3 Notes on Starting Transfer ...............................
....................................................................... 1412
38.5.4 Notes on the SPRF and SPTEF flags ...................................................................................... 1412
39. CRC Calculator (CRC) ............................................................................................................... 1413
39.1 Overview ......................................................................................................................................... 1413
39.2 Register Descriptions ....................................................................................................................... 1414
39.2.1 CRC Control Register (CRCCR) ............................................................................................ 1414
39.2.2 CRC Data Input Register (CRCDIR) ..................................................................................... 1414
39.2.3 CRC Data Output Register (CRCDOR) ................................................................................. 1415
39.3 Operation ......................................................................................................................................... 1416
39.4 Usage Notes ..................................................................................................................................... 1419
39.4.1 Module Stop Function Setting ................................................................................................ 1419
39.4.2 Note on Transmission ............................................................................................................. 1419
40. SD Host Interface (SDHIa) ......................................................................................................... 1420
40.1 Overview ......................................................................................................................................... 1420
40.2 Register Details ................................................................................................................................ 1421
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