Renesas RX Series

40.2.1 Command Register (SDCMD) ............................................................................................... 1421
40.2.2 Argument Register (SDARG) ................................................................................................ 1423
40.2.3 Data Stop Register (SDSTOP) ............................................................................................... 1423
40.2.4 Block Count Register (SDBLKCNT) ..................................................................................... 1424
40.2.5 Response Register 10 (SDRSP10), Response Register 32 (SDRSP32),
Response Register 54 (SDRSP54), Response Register 76 (SDRSP76) ................................. 1425
40.2.6 SD Status Register 1 (SDSTS1) ............................................................................................. 1426
40.2.7 SD Status Register 2 (SDSTS2) ............................................................................................. 1429
40.2.8 SD Interrupt Mask Register 1 (SDIMSK1) ............................................................................ 1433
40.2.9 SD Interrupt Mask Register 2 (SDIMSK2) ............................................................................ 1434
40.2.10 SDHI Clock Control Register (SDCLKCR) ........................................................................... 1435
40.2.11 Transfer Data Size Register (SDSIZE) ................................................................................... 1436
40.2.12 Card Access Option Register (SDOPT) ................................................................................. 1437
40.2.13 SD Error Status Register 1 (SDERSTS1) ............................................................................... 1438
40.2.14 SD Error Status Register 2 (SDERSTS2) ............................................................................... 1439
40.2.15 SD Buffer Register (SDBUFR) .............................................................................................. 1440
40.2.16 SDIO Mode Control Register (SDIOMD) .............................................................................. 1440
40.2.17 SDIO Status Register (SDIOSTS) .......................................................................................... 1442
40.2.18 SDIO Interrupt Mask Register (SDIOIMSK) ......................................................................... 1443
40.2.19 DMA Transfer Enable Register (SDDMAEN) ...................................................................... 1444
40.2.20 SDHI Software Reset Register (SDRST) ............................................................................... 1445
40.2.21 Swap Control Register (SDSWAP) ........................................................................................ 1446
40.3 SDHI Operation ............................................................................................................................... 1447
40.3.1 Data Block Format of the SD Card ........................................................................................ 1447
40.3.2 SD Buffer and the SDBUFR Register .................................................................................... 14
48
40.
3.3 SD Card Detection .................................................................................................................. 1449
40.3.3.1 Using the SDHI_CD Pin to Detect an SD Card ............................................................ 1449
40.3.3.2 Using the SDHI_D3 Pin to Detect an SD Card ............................................................. 1449
40.3.4 SD Card Write Protection ....................................................................................................... 1450
40.3.4.1 Using the SDHI_WP Pin to Enable Write Protection ................................................... 1450
40.3.4.2 Using a Command to Enable Write Protection ............................................................. 1450
40.3.5 Communication Errors and Timeouts ..................................................................................... 1451
40.3.6 Examples of Issuing a Command ........................................................................................... 1452
40.3.6.1 Command Absent of Response Reception and Data Transfer ...................................... 1452
40.3.6.2 Command Absent of Data Transfer ............................................................................... 1453
40.3.6.3 Single Block Read Command (CMD17) ....................................................................... 1454
40.3.6.4 Single Block Write Command (CMD24) ...................................................................... 1456
40.3.6.5 Multi-Block Read Command (CMD18) ........................................................................ 1458
40.3.6.6 Multi-Block Write Command (CMD25) ....................................................................... 1460
40.3.6.7 IO_RW_DIRECT Command (CMD52) ........................................................................ 1462
40.3.6.8 IO_RW_EXTENDED Command (CMD53 (Multi-Block Read)) ................................ 1463