R01UH0823EJ0100 Rev.1.00 Page 401 of 1823
Jul 31, 2019
RX23W Group 19. Data Transfer Controller (DTCa)
Figure 19.13 Example of Operation When Transfer Information Read Skip is Executed
(Vector, Transfer Information, and Transfer Destination Data on the RAM, and Transfer Source
Data on the Peripheral Module)
System clock
ICU.IRn
DTC transfer request
DTC access
Vector read
Transfer
information read
Data
transfer
Transfer
information write
Read skip enable
Data
transfer
Transfer
information write
(2)
R
(1)
n = Vector number
Note: When request sources (vector numbers) of (1) and (2) are the same and the DTCCR.RRS bit is 1, the transfer information read for
request (2) is skipped.
R WR W
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