R01UH0823EJ0100 Rev.1.00 Page 555 of 1823
Jul 31, 2019
RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a)
(c) Initial Setting
In complementary PWM mode, there are six registers that require initial setting. In addition, there is a register that
specifies whether to generate dead time (it should be used only when dead time generation should be disabled).
Before setting complementary PWM mode with the TMDR.MD[3:0] bits, initial values should be set in the following
registers.
The MTU3.TGRC register operates as the buffer register for the MTU3.TGRA register, and should be set with 1/2 the
PWM cycle + dead time Td. The TCBR register operates as the buffer register for the TCDR register, and should be set
with 1/2 the PWM cycle. Set dead time Td in the TDDR register.
When dead time is not needed, the TDER.TDER bit should be set to 0, registers MTU3.TGRC and MTU3.TGRA should
be set to 1/2 the PWM cycle + 1, and the TDDR register should be set to 1.
Set the respective initial PWM duty values in three buffer registers MTU3.TGRD, MTU4.TGRC, and MTU4.TGRD.
The values set in the five buffer registers excluding the TDDR register are transferred to the corresponding compare
registers as soon as complementary PWM mode is set.
Set the MTU4.TCNT counter to 0000h before setting complementary PWM mode.
Note: The value set in the MTU3.TGRC register should be the sum of 1/2 the PWM cycle set in the TCBR register and dead time Td
set in the TDDR register. When dead time generation is disabled by the TDER register, the TGRC register should be set to 1/2
the PWM cycle + 1.
(d) PWM Output Level Setting
In complementary PWM mode, the PWM output level is set with bits OLSN and OLSP in the TOCR1 register or bits
OLS1P to OLS3P and OLS1N to OLS3N in the TOCR2 register.
The output level can be set for each of the three positive phases and three negative phases of 6-phase output.
Complementary PWM mode should be cleared before setting or changing output levels.
(e) Dead Time Setting
In complementary PWM mode, dead time can be set for PWM output.
The dead time is set in the TDDR register. The value set in the TDDR register is used as the MTU3.TCNT counter start
value and creates a dead time between counters MTU3.TCNT and MTU4.TCNT. Complementary PWM mode should be
cleared before changing the contents of the TDDR register.
(f) Dead Time Suppressing
Dead time generation is suppressed by setting the TDER.TDER bit to 0. The TDER bit can be set to 0 only when 0 is
written to it after reading it as 1.
Registers MTU3.TGRA and MTU3.TGRC should be set to 1/2 PWM cycle + 1 and the TDDR register should be set to 1.
By the above settings, PWM waveforms without dead time can be obtained.
Figure 23.41 shows an example of
operation without dead time.
Table 23.53 Registers and Counters Requiring Initial Setting
Register and Counter Setting
MTU3.TGRC 1/2 PWM cycle + dead time Td
(1/2 PWM cycle + 1 when dead time generation is disabled by the TDER register)
TDDR Dead time Td (1 when dead time generation is disabled by the TDER register)
TCBR 1/2 PWM cycle
MTU3.TGRD,
MTU4.TGRC,
MTU4.TGRD
Initial PWM duty value for each phase
MTU4.TCNT 0000h
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