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R01UH0823EJ0100 Rev.1.00 Page 642 of 1823

Jul 31, 2019

RX23W Group 24. Port Output Enable 2 (POE2a)

Table 24.2 lists I/O pins to be used by the POE.

Table 24.3 lists output-level comparisons with pin combinations.

Table 24.2 POE I/O Pins

Pin Name I/O Description

POE0#, POE1#,

POE3#

Input Request signals to place the pins for MTU complementary PWM output in high-impedance.

POE8# Input Request signal to place the MTU0 output pins in high-impedance.

MTIOC3B Output MTU3 complementary PWM output pin

MTIOC3D Output MTU3 complementary PWM output pin

MTIOC4A Output MTU4 complementary PWM output pin

MTIOC4B Output MTU4 complementary PWM output pin

MTIOC4C Output MTU4 complementary PWM output pin

MTIOC4D Output MTU4 complementary PWM output pin

MTIOC0A Output MTU0 output pin

MTIOC0B Output MTU0 output pin

MTIOC0C Output MTU0 output pin

Table 24.3 Pin Combinations

Pin Combination I/O Description

MTIOC3B and MTIOC3D Output Pin combinations for output-level comparison and high-impedance control can be selected

by POE registers.

The pins for MTU complementary PWM output are placed in high-impedance when the pins

simultaneously output an active level for one or more PCLK clock cycles.

(When the MTU.TOCR1.TOCS bit = 0:

The active level is low level if the MTU.TOCR1.OLSP and OLSN bits are 0, and the active

level is high level if the MTU.TOCR1.OLSP and OLSN bits are 1.

When the MTU.TOCR1.TOCS bit = 1:

The active level is low level if the MTU.TOCR2.OLS3N, OLS3P, OLS2N, OLS2P, OLS1N,

and OLS1P bits are 0, and the active level is high level if the MTU.TOCR2.OLS3N, OLS3P,

OLS2N, OLS2P, OLS1N, and OLS1P bits are 1.)

MTIOC4A and MTIOC4C Output

MTIOC4B and MTIOC4D Output

Renesas RX Series User Manual

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