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R01UH0823EJ0100 Rev.1.00 Page 667 of 1823

Jul 31, 2019

RX23W Group 25. 16-Bit Timer Pulse Unit (TPUa)

TPU has two TIORH registers, one for TPU0 and TPU3, and one TIORL register for TPU3, and also has four TIOR

registers, one for TPU1, TPU2, TPU4, and TPU5. Thus the TPU has seven timer I/O control registers in total.

TIORH, TIORL, and TIOR control registers TGRA, TGRB, TGRC, and TGRD.

Note that TIORH, TIORL, and TIOR are affected by the TMDR setting. For details, see

Table 25.13 to Table 25.19.

The initial output specified by TIORH, TIORL, and TIOR is valid when the counter is stopped (the TPU.TSTR.CSTj bit

(j = 0 to 5) is cleared to 0). In PWM mode 2, the output at the time when the TCNT is cleared to 0 is specified as the

initial output.

When buffer operation has been selected for register TGRC or TGRD, the settings of the IOC[3:0] or IOD[3:0] bits

become ineffective, and the TGRC or TGRD register simply operates as a buffer.

To specify the input capture pin in TIORH, TIORL, or TIOR, set the bit in the port direction register (PDR) for the

corresponding pin to 0 (input port), and set the bit in the port mode register (PMR) to 1 (uses the pin as an I/O port for

peripheral functions). For details, see

section 21, I/O Ports.

IOA[3:0] Bits (TGRA Control)

Select the function of TPUm.TGRA (m = 3, 4).

IOB[3:0] Bits (TGRB Control)

Select the function of TPUm.TGRB (m = 0 to 5).

IOC[3:0] Bits (TGRC Control)

Select the function of TPUm.TGRC (m = 3).

IOD[3:0] Bits (TGRD Control)

Select the function of TPUm.TGRD (m = 3).

Renesas RX Series User Manual

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