R01UH0823EJ0100 Rev.1.00 Page 735 of 1823
Jul 31, 2019
RX23W Group 26. 8-Bit Timer (TMR)
Note 1. To use an external count clock, set the corresponding pin function. For details, refer to section 21, I/O Ports and section 22,
Multi-Function Pin Controller (MPC).
Note 2. If the clock input of TMR0 (TMR2) is the overflow signal of the TMR1.TCNT (TMR3.TCNT) counter and that of TMR1 (TMR3) is
the compare match signal of the TMR0.TCNT (TMR2.TCNT) counter, no TCNT count clock is generated. Do not use this
setting.
Table 26.5 Clock Input to TCNT and Count Condition
Channel
TCCR Register
Description
CSS[1:0] CKS[2:0]
b4 b3 b2 b1 b0
TMR0
(TMR2)
0 0 — 0 0 Clock input prohibited
1 Uses external count clock. Counts at rising edge*
1
.
1 0 Uses external count clock. Counts at falling edge*
1
.
1 Uses external count clock. Counts at both rising and falling edges*
1
.
01000Uses internal clock. Counts at PCLK.
1 Uses internal clock. Counts at PCLK/2.
1 0 Uses internal clock. Counts at PCLK/8.
1 Uses internal clock. Counts at PCLK/32.
1 0 0 Uses internal clock. Counts at PCLK/64.
1 Uses internal clock. Counts at PCLK/1024.
1 0 Uses internal clock. Counts at PCLK/8192.
1 Clock input prohibited
1 0 — — — Setting prohibited
1 1 — — — Counts at TMR1.TCNT (TMR3.TCNT) overflow signal*
2
.
TMR1
(TMR3)
0 0 — 0 0 Clock input prohibited
1 Uses external count clock. Counts at rising edge*
1
.
1 0 Uses external count clock. Counts at falling edge*
1
.
1 Uses external count clock. Counts at both rising and falling edges*
1
.
01000Uses internal clock. Counts at PCLK.
1 Uses internal clock. Counts at PCLK/2.
1 0 Uses internal clock. Counts at PCLK/8.
1 Uses internal clock. Counts at PCLK/32.
1 0 0 Uses internal clock. Counts at PCLK/64.
1 Uses internal clock. Counts at PCLK/1024.
1 0 Uses internal clock. Counts at PCLK/8192.
1 Clock input prohibited
1 0 — — — Setting prohibited
1 1 — — — Counts at TMR0.TCNT (TMR2.TCNT) compare match A*
2
.
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