Renesas RX Series

R01UH0823EJ0100 Rev.1.00 Page 862 of 1823
Jul 31, 2019
RX23W Group 32. USB 2.0 Host/Function Module (USBc)
FIFO Port Bit
Accessing the FIFO port bits allows reading the received data from the FIFO buffer or writing the transmit data to the
FIFO buffer.
Each FIFO port register can be accessed only while the FRDY flag in each FIFO port control register (CFIFOCTR,
D0FIFOCTR, or D1FIFOCTR) is 1.
The valid bits in a FIFO port register depend on the settings of the corresponding MBW bit of the FIFO port select
register (CFIFOSEL, D0FIFOSEL, or D1FIFOSEL).
When the MBW bit is 1 (16-bit width), the data arrangement may differ from the data arrangement on the RAM
depending on the value of the MDE.MDE[2:0] bits and the setting of the BIGEND bit (CFIFOSEL.BIGEND,
D0FIFOSEL.BIGEND, or D1FIFOSEL.BIGEND).
Table 32.5 lists the endian operation in 16-bit access. Note that if
the total number of transmit data bytes is odd, access the L[7:0] bits in bytes when writing the last data.
When the MBW bit is 0 (8-bit width), access the L[7:0] bits in bytes.
Table 32.5 Endian Operation in 16-Bit Access
MDE.MDE[2:0] bits
CFIFOSEL.BIGEND Bit
D0FIFOSEL.BIGEND Bit
D1FIFOSEL.BIGEND Bit Bits 15 to 8 Bits 7 to 0 Remarks
000b (big endian) 0 (little endian) Data in address N + 1 Data in address N Bytes reversed
1 (big endian) Data in address N Data in address N + 1
111b (little endian) 0 (little endian) Data in address N + 1 Data in address N
1 (big endian) Data in address N Data in address N + 1 Bytes reversed