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Renesas RX Series User Manual

Renesas RX Series
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R01UH0823EJ0100 Rev.1.00 Page 924 of 1823
Jul 31, 2019
RX23W Group 32. USB 2.0 Host/Function Module (USBc)
(3) When the SOFCFG.BRDYM Bit = 1 and the PIPECFG.BFRE Bit = 0
With these settings, the BRDYSTS.PIPEnBRDY values are linked to the BSTS flag setting for each pipe. In other words,
the BRDY interrupt status flags (PIPEnBRDY) are set to 1 or 0 by the USB depending on the FIFO buffer status.
(a) For the pipe in the transmitting direction:
The BRDY interrupt status bits are set to 1 when the FIFO buffer is ready for write access, and are set to 0 when it
is not ready.
However, the BRDY interrupt is not generated even if the DCP in the transmitting direction is ready for write
access.
(b) For the pipe in the receiving direction:
The BRDY interrupt status bits are set to 1 when the FIFO buffer is ready for read access, and are set to 0 when all
data have been read (not ready for read access).
When a zero-length packet is received while the FIFO buffer is empty, the pertinent bit is set to 1 and the BRDY
interrupt is continuously generated until BCLR = 1 is written through software.
With this setting, the PIPEnBRDY flag cannot be set to 0 through software.
When the SOFCFG.BRDYM bit is set to 1, all PIPECFG.BFRE bits (for all pipes) should be set to 0.

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Renesas RX Series Specifications

General IconGeneral
CoreRXv1, RXv2, RXv3
Flash MemoryUp to 8 MB
RAMUp to 1 MB
Operating Voltage1.62V to 5.5V
Operating Temperature-40°C to +85°C or +105°C
PackageBGA, LQFP
ADC Resolution12-bit
DAC Resolution12-bit
Communication InterfacesSCI, SPI, I2C, USB, Ethernet, CAN
Architecture32-bit
Security FeaturesMemory Protection Unit (MPU)

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