Renesas RX Series

R01UH0823EJ0100 Rev.1.00 Page 950 of 1823
Jul 31, 2019
RX23W Group 32. USB 2.0 Host/Function Module (USBc)
 When the IITV[2:0] ≠ 000b: The interval counting starts on completion of successful reception of the first data
packet after the PID[1:0] bits for the selected pipe have been modified to 01b (BUF).
Figure 32.17 Relationship between Frames and Expected Token Reception When IITV[2:0] ≠ 000b
(b) When the selected pipe is for isochronous IN transfers
The PIPEPERI.IFIS bit should be 1 for this use. When IFIS = 0, the USB transmits a data packet in response to the
received IN token irrespective of the setting of the PIPEPERI.IITV[2:0] bits.
When IFIS = 1, the USB clears the FIFO buffer when the USB fails to receive an IN token in the frame at the interval set
by the IITV[2:0] bits while there is data to be transmitted in the FIFO buffer.
The USB also clears the FIFO buffer when the USB fails to receive an IN token successfully because of a bus error such
as a CRC error contained in the IN token.
The FIFO buffer is cleared at the timing of SOF packet reception. Even if the SOF packet is corrupted, the internal
interpolation allows the FIFO buffer to be cleared at the timing to receive the SOF packet.
The timing to start interval counting depends on the setting of the IITV[2:0] bits (similar to the timing during OUT
transfers).
The interval is counted on any of the following conditions in function controller mode.
 When a hardware-reset is applied to the USB (here, the IITV[2:0] bits are also set to 000b).
 When the PIPEnCTR.ACLRM bit is set to 1 by software.
 When the USB detects a USB bus reset.
USB bus
PID bit setting
Token
NAK BUF BUF BUF
Token
reception
is not waited
Interval counter started
BUF BUF BUF
Token
reception
is not waited
Token
reception
is waited
Token
reception
is not waited
Token
reception
is waited
Token
reception
is not waited
Token
reception
is waited
OUT
DATA
OUT
DATA
OUT
DATA
SOF SOF SOF SOF SOF SOF SOF