Renesas RX Series User Manual

R01UH0823EJ0100 Rev.1.00 Page 987 of 1823
Jul 31, 2019
RX23W Group 33. Serial Communications Interface (SCIg, SCIh)
BCP2 Bit (Base Clock Pulse 2)
Selects the number of base clock cycles in a 1-bit data transfer time in smart card interface mode. Set this bit in
combination with the SMR.BCP[1:0] bits.
Note 1. S is the value of S in BRR (refer to section 33.2.11, Bit Rate Register (BRR)).
Table 33.9 Combinations of the SCMR.BCP2 Bit and SMR.BCP[1:0] Bits
SCMR.BCP2 Bit SMR.BCP[1:0] Bits Number of Base Clock Cycles for 1-Bit Transfer Period
0 0 0 93 clock cycles (S = 93)*
1
0 0 1 128 clock cycles (S = 128)*
1
0 1 0 186 clock cycles (S = 186)*
1
0 1 1 512 clock cycles (S = 512)*
1
1 0 0 32 clock cycles (S = 32)*
1
(Initial Value)
1 0 1 64 clock cycles (S = 64)*
1
1 1 0 372 clock cycles (S = 372)*
1
1 1 1 256 clock cycles (S = 256)*
1

Renesas RX Series Specifications

General

Brand	Renesas
Model	RX Series
Category	Microcontrollers
Language	English