ADSP-21368 SHARC Processor Hardware Reference 3-43
External Port
SDRAM power-up sequence start.
SDPSS bit 14. The SDPM bit specifies
the power-up mode and the SDPSS bit starts an SDRAM power-up (initial-
ization) sequence. When this bit is set (=1), the SDRAM power-up
sequence starts on the next SDRAM access. When cleared, this bit has no
effect. This bit always reads zero. See also “Load Mode Register” on
page 3-64.
SDRAM self-refresh command. SDSRF bit 15. When set (=1), starts the
self-refresh mode. When cleared (=0) this bit has no effect. This bit always
reads zero. In self-refresh mode, the SDRAM performs refresh operations
internally which reduces the SDRAM’s power consumption.
When SDSRF is set to 1, the SDC enters an idle state. In this state, it issues
a precharge command (if necessary) and then issues a self-refresh com-
mand. If an internal access is pending, the SDC delays issuing the
self-refresh command until it completes all pending SDRAM access
requests. Once the SDRAM device enters into self-refresh mode, the
SDRAM controller asserts the SDSRA bit in the SDRAM control status reg-
ister (SDSTAT). The SDRAM controller ignores other self-refresh requests
when the SDRAM device is already in self-refresh mode.
L
The SDRAM device exits self-refresh mode only when the SDC
receives a request for SDRAM space access. There is no way to can-
cel entry into self-refresh mode.
SDRAM external data path width.
X16DE bit 16. Selects whether the
SDRAM interface is 32 or 16 bits wide.
• If set (=1), a 16-bit SDRAM should be used;
DATA[15–0] should be connected to the SDRAM data pins;
ADDR[14:0] should be connected to SDRAM address pins 14–0;
16 to 32-bit packing is performed.
Note that ADDR[18:17] pins are also used. See tables Table 3-22 on
page 3-53 to Table 3-25 on page 3-57 for bank address usage.
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