Analog Devices SHARC ADSP-21368 - Page 892

Index
I-36 ADSP-21368 SHARC Processor Hardware Reference
U
UART, 11-1
assigning interrupt priority, 11-11
baud rate, 11-4, 11-5
baud rate examples, 11-12
data ready flag, 11-13
data word, 11-4
divisor, 11-11, A-125
divisor reset, 11-12
DMA channel latency requirement, 2-44
DMA channels, 2-44
DMA mode, 2-44
interrupt conditions, 11-9
non-DMA mode, 11-13
restrictions, 11-11
sampling clock period, 11-6
sampling point, 11-6
standard, 1-10, 11-1
system DMA and, 11-7
timers, 11-1
UART bits
9-bit RX enable (RX9), A-127
9-bit TX enable (TX9), A-127
address detect enable (UARTAEN),
A-127
data ready (DR), 11-4
DMA TX/RX control, A-128
DMA TX/RX status, A-129
enable receive buffer full interrupt
(UARTRBFIE), 11-7, A-123
enable transmit buffer empty interrupt
(UARTTBEIE), 11-7, A-123
interrupt enable, A-123
packing enable (PACK), A-127
pin status (UARTPSTx), A-127
synch data packing in RX
(UARTPKSYN), A-127
THR register empty (UARTTHRE),
11-4, A-120
UART bits (continued)
TSR and UARTxTHR empty
(UARTTEMT), 11-4
UARTNOINT (pending interrupt),
A-124
UARTSTAT (interrupt), A-124
UART registers
divisor latch (UARTxDLH), 11-11,
A-125
divisor latch register
(UARTxDLL), 11-11, A-125
DMA control, 2-27
interrupt enable register (UARTxIER),
11-7, A-123
interrupt identification register
(UARTxIIR), 11-9, A-124
line control register (UARTxLCR), 11-3,
A-118
line status register (UARTxLSR), 11-4,
A-120
receive buffer register (UARTxRBR),
11-5, A-122
scratch register (UARTxSCR), 11-12,
A-126
shadow, A-122
transmit holding (UARTxTHR), 11-4,
11-5, A-121
transmit shift register (UART_TSR),
11-4
UARTxDLH (divisor latch register),
11-11, A-125
UARTxDLL (divisor latch register),
11-11, A-125
UARTxIER (interrupt enable register),
11-7, A-123
UARTxIIR (interrupt identification
register), 11-9, A-124
UARTxLCR (line control register), 11-3,
A-118