Renesas RX Series User Manual

R01UH0823EJ0100 Rev.1.00 Page 1307 of 1823
Jul 31, 2019
RX23W Group 37. Serial Sound Interface (SSI)
(1) When PDTA bit is 0
(2) When PDTA bit is 1
SCKP Bit (Serial Bit Clock Polarity)
This bit is used to select the polarity of SSISCK0 signal.
Table 37.4 lists the setting of SCKP bit and signal I/O timing.
CHNL[1:0] Bits (Channels)
These bits select the number of channels to be decoded in each system word. Set these bits to 00b in this module.
Table 37.4 Setting of SCKP Bit and Signal Timing
SCKP Bit = 0 SCKP Bit = 1
SSIRXD0 input sampling timing for reception SSISCK0 rising edge SSISCK0 falling edge
SSITXD0 output changing timing for transmission SSISCK0 falling edge SSISCK0 rising edge
SSIWS0 input sampling timing in slave mode (SWSD bit = 0) SSISCK0 rising edge SSISCK0 falling edge
SSIWS0 output changing timing in master mode (SWSD bit = 1) SSISCK0 falling edge SSISCK0 rising edge
DWL[2:0] Bits
000b
001b
010b
011b
100b
101b
SSIFTDR and SSIFRDR Registers
4th word 3rd word 2nd word 1st word
31 24 23 16 15 8 7 0
2nd word 1st word
31 16 15 0
Valid Invalid
31 14 13 0
Valid Invalid
31 12 11 0
Valid Invalid
31 10 9 0
Valid Invalid
31 8 7 0
DWL[2:0] Bits
000b
001b
010b
011b
100b
101b
SSIFTDR and SSIFRDR Registers
1st word 2nd word 3rd word 4th word
31 24 23 16 15 8 7 0
1st word 2nd word
31 16 15 0
Invalid Valid
31 18 17 0
Invalid Valid
31 20 19 0
Invalid Valid
31 22 21 0
Invalid Valid
31 24 23 0

Renesas RX Series Specifications

General

Brand	Renesas
Model	RX Series
Category	Microcontrollers
Language	English