To Next Page

To Previous Page

R01UH0823EJ0100 Rev.1.00 Page 1373 of 1823

Jul 31, 2019

RX23W Group 38. Serial Peripheral Interface (RSPIa)

(3) LSB First Transfer (32-Bit Data)

Figure 38.20 shows details of operations by the RSPI data register (SPDR) and the shift register in transfer with parity

enabled, an RSPI data length of 32 bits, and LSB first selected.

In transmission, the value of the parity bit (P) is calculated from bits T30 to T00. This replaces the final bit, T31, and the

whole is copied to the shift register. Data are transmitted in the order T00, T01, …, T30, and P.

In reception, received data are shifted in bit by bit through bit 0 of the shift register. When bits R00 to P have been

collected after input of the required number of cycles of RSPCK, the value in the shift register is copied to the receive

buffer. On copying of data to the shift register, the data from R00 to P are checked by judging the parity.

Figure 38.20 LSB First Transfer (32-Bit Data, Parity Enabled)

Transfer start

Transfer end

T31 T30 T29 T28 T27 T26 T25 T24 T23 T06 T05 T04 T03 T02 T01 T00

T00 T01 T02 T03 T04 T05 T06 T07 T08 T25 T26 T27 T28 T29 T30 P

R00 R01 R02 R03 R04 R05 R06 R07 R08 R25 R26 R27 R28 R29 R30 P

P R30 R29 R28 R27 R26 R25 R24 R23 R06 R05

R23 R24

R08 R07 R04 R03 R02 R01 R00

T08 T07

T23 T24

Shift register

Input

Output

Copy

Bit 0

Receive buffer

Bit 31

Transmit buffer

Bit 0Bit 31

P T30 T29 T28 T27 T26 T25 T24 T23 T06 T05 T04 T03 T02 T01 T00

T08 T07

Bit 0Bit 31

Parity added

Parity calculated

Note: Output = MOSI (master)/MISO (slave), input = MISO (master)/MOSI (slave)

Renesas RX Series User Manual

Questions and Answers: