Renesas RX Series User Manual

R01UH0823EJ0100 Rev.1.00 Page 358 of 1823
Jul 31, 2019
RX23W Group 18. DMA Controller (DMACA)
(2) Repeat Transfer Mode
In repeat transfer mode, one data is transferred by one transfer request.
A maximum of 1K data can be set as a total repeat transfer size using DMCRA of the DMACm.
A maximum of 1K can be set as the number of repeat transfer operations using DMCRB of the DMACm; therefore, a
maximum of 1M data (1K data × 1K count of repeat transfer operations) can be set as a total data transfer size.
Either the transfer source or transfer destination can be specified as a repeat area. When transfer of the repeat size data is
completed, the address of the specified repeat area (DMSAR or DMDAR of the DMACm) returns to the transfer start
address. When data of the specified repeat size has all been transferred in repeat transfer mode, DMA transfer can be
stopped and the repeat size end interrupt can be requested. DMA transfer can be resumed by writing 1 to the DTE bit in
DMCNT of DMACm in the repeat size end interrupt handling.
A transfer end interrupt request can be generated after completion of the specified number of repeat transfer operations.
Table 18.4 summarizes the register update operation in repeat transfer mode, and Figure 18.3 shows the operation in
repeat transfer mode.
Note 1. Offset addition can be specified only for DMAC0.
Table 18.4 Register Update Operation in Repeat Transfer Mode
Register Function
Update Operation after Completion of a Transfer by One Transfer Request
When DMACm.DMCRAL is not 1
When DMACm.DMCRAL is 1
(Transfer of the Last Data in Repeat Size)
DMACm.DMSAR Transfer source
address
Increment/decrement/fixed/offset
addition*
1
 DMACm.DMTMD.DTS[1:0] = 00b
Increment/decrement/fixed/offset addition*
1
 DMACm.DMTMD.DTS[1:0] = 01b
Initial value of DMACm.DMSAR
 DMACm.DMTMD.DTS[1:0] = 10b
Increment/decrement/fixed/offset addition*
1
DMACm.DMDAR Transfer
destination
address
Increment/decrement/fixed/offset
addition*
1
 DMACm.DMTMD.DTS[1:0] = 00b
Initial value of DMACm.DMDAR
 DMACm.DMTMD.DTS[1:0] = 01b
Increment/decrement/fixed/offset addition*
1
 DMACm.DMTMD.DTS[1:0] = 10b
Increment/decrement/fixed/offset addition*
1
DMACm.DMCRAH Repeat size Not updated Not updated
DMACm.DMCRAL Transfer count Decremented by one DMACm.DMCRAH
DMACm.DMCRB Count of repeat
transfer operations
Not updated Decremented by one

Renesas RX Series Specifications

General

Core	RXv1, RXv2, RXv3
Flash Memory	Up to 8 MB
RAM	Up to 1 MB
Operating Voltage	1.62V to 5.5V
Operating Temperature	-40°C to +85°C or +105°C
Package	BGA, LQFP
ADC Resolution	12-bit
DAC Resolution	12-bit
Communication Interfaces	SCI, SPI, I2C, USB, Ethernet, CAN
Architecture	32-bit
Security Features	Memory Protection Unit (MPU)