Renesas RX Series User Manual

R01UH0823EJ0100 Rev.1.00 Page 360 of 1823
Jul 31, 2019
RX23W Group 18. DMA Controller (DMACA)
(3) Block Transfer Mode
In block transfer mode, a single block data is transferred by one transfer request.
A maximum of 1K data can be set as a total block transfer size using DMCRA of the DMACm.
A maximum of 1K can be set as the number of block transfer operations using DMCRB of the DMACm; therefore, a
maximum of 1M data (1K data × 1K count of block transfer operations) can be set as a total data transfer size.
Either the transfer source or transfer destination can be specified as a block area. When transfer of a single block data is
completed, the address of the specified block area (DMSAR or DMDAR of the DMACm) returns to the transfer start
address. When a single block data has all been transferred in block transfer mode, DMA transfer can be stopped and the
repeat size end interrupt can be requested. DMA transfer can be resumed by writing 1 to the DTE bit in DMCNT of
DMACm in the repeat size end interrupt handling.
Transfer end interrupt request can be generated after completion of the specified number of block transfer operations.
Table 18.5 summarizes the register update operation in block transfer mode, and Figure 18.4 shows the operation in
block transfer mode.
Note 1. Offset addition can be specified only for DMAC0.
Figure 18.4 Operation in Block Transfer Mode
Table 18.5 Register Update Operation in Block Transfer Mode
Register Function
Update Operation after Completion of Single-Block Transfer by
One Transfer Request
DMACm.DMSAR Transfer source address  DMACm.DMTMD.DTS[1:0] = 00b
Increment/decrement/fixed/offset addition*
1
 DMACm.DMTMD.DTS[1:0] = 01b
Initial value of DMACm.DMSAR
 DMACm.DMTMD.DTS[1:0] = 10b
Increment/decrement/fixed/offset addition*
1
DMACm.DMDAR Transfer destination
address
 DMACm.DMTMD.DTS[1:0] = 00 b
Initial value of DMACm.DMDAR
 DMACm.DMTMD.DTS[1:0] = 01 b
Increment/decrement/fixed/offset addition*
1
 DMACm.DMTMD.DTS[1:0] = 10 b
Increment/decrement/fixed/offset addition*
1
DMACm.DMCRAH Block size Not updated
DMACm.DMCRAL Transfer count DMACm.DMCRAH
DMACm.DMCRB Count of block transfer
operations
Decremented by one
Transfer source data area
Transfer destination data area
(Specified as a block area)
Block area
DMDAR
DMSAR
Transfer
N-th block
First block

Renesas RX Series Specifications

General

Core	RXv1, RXv2, RXv3
Flash Memory	Up to 8 MB
RAM	Up to 1 MB
Operating Voltage	1.62V to 5.5V
Operating Temperature	-40°C to +85°C or +105°C
Package	BGA, LQFP
ADC Resolution	12-bit
DAC Resolution	12-bit
Communication Interfaces	SCI, SPI, I2C, USB, Ethernet, CAN
Architecture	32-bit
Security Features	Memory Protection Unit (MPU)