Renesas RX Series

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R01UH0823EJ0100 Rev.1.00 Page 435 of 1823

Jul 31, 2019

RX23W Group 21. I/O Ports

Figure 21.4 I/O Port Configuration (4)

Port 3: P30, P31

Peripheral module output signal

Reading the port

PMR

ODR0, ODR1

PDR

PODR

Enable peripheral module output

Input signal of peripheral module/interrupt

PCR

ISEL bit

1: ON

0: OFF

RTC time capture event input signal

Reading the port

NMI input signal

Port 3: P35

Note 1. Control signal for N-channel open-drain output.

Internal busInternal bus

Main Page

Table of Contents7
Features51
Overview52
Outline of Specifications52
List of Products57
Block Diagram58
Pin Functions59
Pin Assignments63
Cpu69
Features69
Register Set of the CPU70
General-Purpose Registers (R0 to R15)71
Control Registers71
Interrupt Stack Pointer (Isp)/User Stack Pointer (USP)72
Exception Table Register (EXTB)72
Interrupt Table Register (INTB)72
Program Counter (PC)72
Processor Status Word (PSW)73
Backup PC (BPC)74
Backup PSW (BPSW)75
Fast Interrupt Vector Register (FINTV)75
Floating-Point Status Word (FPSW)76
Accumulator78
Processor Mode79
Supervisor Mode79
User Mode79
Privileged Instruction79
Switching between Processor Modes79
Data Types80
Integer80
Floating-Points81
Bitwise Operations81
Strings82
Endian83
Switching the Endian83
Access to I/O Registers86
Notes on Access to I/O Registers86
Data Arrangement87
Data Arrangement in Registers87
Data Arrangement in Memory87
Notes on the Allocation of Instruction Codes87
Vector Table88
Exception Vector Table88
Interrupt Vector Table89
Operation of Instructions90
Restrictions on RMPA and String-Manipulation Instructions90
Transfer Size and Data Prefetching90
Access to the External Space90
Access to I/O Registers90
Number of Cycles91
Instruction and Number of Cycle91
Numbers of Cycles for Response to Interrupts95
Operating Modes96
Operating Mode Types and Selection96
Register Descriptions97
Mode Monitor Register (MDMONR)97
System Control Register 1 (SYSCR1)98
Details of Operating Modes99
Single-Chip Mode99
Boot Mode99
Boot Mode (USB Interface)99
Boot Mode (SCI)99
Transitions of Operating Modes100
Operating Mode Transitions Determined by the Mode-Setting Pins100
Address Space101
I/O Registers103
I/O Register Addresses (Address Order)105
Resets136
Overview136
Register Descriptions138
Reset Status Register 0 (RSTSR0)138
Reset Status Register 1 (RSTSR1)139
Reset Status Register 2 (RSTSR2)140
Software Reset Register (SWRR)141
Operation142
RES# Pin Reset142
Power-On Reset and Voltage Monitoring 0 Reset142
Voltage Monitoring 1 Reset144
Independent Watchdog Timer Reset145
Watchdog Timer Reset145
Software Reset145
Determination of Cold/Warm Start146
Determination of Reset Generation Source147
Option-Setting Memory (OFSM)148
Overview148
Register Descriptions149
Option Function Select Register 0 (OFS0)149
Option Function Select Register 1 (OFS1)153
Endian Select Register (MDE)154
Usage Note155
Setting Example of Option-Setting Memory155
Voltage Detection Circuit (Lvdab)156
Overview156
Register Descriptions158
Voltage Monitoring 1 Circuit Control Register 1 (LVD1CR1)158
Voltage Monitoring 1 Circuit Status Register (LVD1SR)159
Voltage Monitoring Circuit Control Register (LVCMPCR)160
Voltage Detection Level Select Register (LVDLVLR)161
Voltage Monitoring 1 Circuit Control Register 0 (LVD1CR0)162
VCC Input Voltage Monitor163
Monitoring Vdet0163
Monitoring Vdet1163
Reset from Voltage Monitor 0164
Interrupt and Reset from Voltage Monitoring 1165
Event Link Output167
Interrupt Handling and Event Linking167
Clock Generation Circuit168
Overview168
Register Descriptions172
System Clock Control Register (SCKCR)172
System Clock Control Register 3 (SCKCR3)174
PLL Control Register (PLLCR)175
PLL Control Register 2 (PLLCR2)176
USB-Dedicated PLL Control Register (UPLLCR)177
USB-Dedicated PLL Control Register 2 (UPLLCR2)178
Main Clock Oscillator Control Register (MOSCCR)179
Sub-Clock Oscillator Control Register (SOSCCR)180
Low-Speed On-Chip Oscillator Control Register (LOCOCR)181
IWDT-Dedicated On-Chip Oscillator Control Register (ILOCOCR)182
High-Speed On-Chip Oscillator Control Register (HOCOCR)183
High-Speed On-Chip Oscillator Control Register 2 (HOCOCR2)184
Oscillation Stabilization Flag Register (OSCOVFSR)185
Oscillation Stop Detection Control Register (OSTDCR)187
Oscillation Stop Detection Status Register (OSTDSR)188
Main Clock Oscillator Wait Control Register (MOSCWTCR)189
CLKOUT Output Control Register (CKOCR)190
Main Clock Oscillator Forced Oscillation Control Register (MOFCR)191
Memory Wait Cycle Setting Register (MEMWAIT)192
Low-Speed On-Chip Oscillator Trimming Register (LOCOTRR)194
IWDT-Dedicated On-Chip Oscillator Trimming Register (ILOCOTRR)194
High-Speed On-Chip Oscillator Trimming Register N (Hocotrrn) (N = 0, 3)195
Main Clock Oscillator196
Connecting a Crystal196
External Clock Input197
Handling of Pins When the Main Clock Is Not Used197
Notes on the External Clock Input197
Sub-Clock Oscillator198
Connecting 32.768-Khz Crystal198
Handling of Pins When Sub-Clock Is Not Used199
Dedicated Clock Oscillator for Bluetooth200
Connecting the Oscillator200
Connecting the Bluetooth-Dedicated Clock Output Pin200
Oscillation Stop Detection Function201
Oscillation Stop Detection and Operation after Detection201
Oscillation Stop Detection Interrupts202
PLL Circuit203
Internal Clock203
System Clock203
Peripheral Module Clock203
Flashif Clock203
USB Clock204
CAN Clock204
CAC Clock204
RTC-Dedicated Clock204
IWDT-Dedicated Clock204
SSI Clock204
Clocks for BLE204
Low-Power Timer Clock204
Usage Notes205
Notes on Clock Generation Circuit205
Notes on Resonator205
Notes on Board Design205
Notes on Resonator Connection Pins206
Notes on Sub-Clock206
Clock Frequency Accuracy Measurement Circuit (CAC)210
Overview210
Register Descriptions212
CAC Control Register 0 (CACR0)212
CAC Control Register 1 (CACR1)213
CAC Control Register 2 (CACR2)214
CAC Interrupt Request Enable Register (CAICR)215
CAC Status Register (CASTR)216
CAC Upper-Limit Value Setting Register (CAULVR)217
CAC Lower-Limit Value Setting Register (CALLVR)217
CAC Counter Buffer Register (CACNTBR)217
Operation218
Measuring Clock Frequency218
Digital Filtering of Signals on the CACREF Pin219
Interrupt Requests219
Usage Notes220
Module Stop Function Setting220
Low Power Consumption221
Overview221
Register Descriptions225
Standby Control Register (SBYCR)225
Module Stop Control Register a (MSTPCRA)226
Module Stop Control Register B (MSTPCRB)227
Module Stop Control Register C (MSTPCRC)229
Module Stop Control Register D (MSTPCRD)230
Operating Power Control Register (OPCCR)231
Sub Operating Power Control Register (SOPCCR)232
Sleep Mode Return Clock Source Switching Register (RSTCKCR)237
Reducing Power Consumption by Switching Clock Signals239
Module Stop Function239
Function for Lower Operating Power Consumption239
Setting Operating Power Control Mode239
Low Power Consumption Modes241
Sleep Mode241
Entry to Sleep Mode241
Exit from Sleep Mode242
Sleep Mode Return Clock Source Switching Function242
Deep Sleep Mode243
Entry to Deep Sleep Mode243
Exit from Deep Sleep Mode244
Software Standby Mode245
Entry to Software Standby Mode245
Exit from Software Standby Mode246
Example of Software Standby Mode Application247
Usage Notes248
I/O Port States248
Module Stop State of DMAC and DTC248
On-Chip Peripheral Module Interrupts248
Write Access to MSTPCRA, MSTPCRB, MSTPCRC, and MSTPCRD248
Timing of WAIT Instructions248
Rewrite the Register by DMAC and DTC in Sleep Mode248
Battery Backup Function249
Overview249
Register Descriptions250
VBATT Control Register (VBATTCR)250
VBATT Status Register (VBATTSR)251
VBATT Pin Voltage Drop Detection Interrupt Control Register (VBTLVDICR)252
Operation253
Battery Backup Function253
VBATT Pin Voltage Monitoring Function254
Usage Notes255
Register Write Protection Function256
Register Descriptions257
Protect Register (PRCR)257
Exception Handling258
Exception Events258
Undefined Instruction Exception259
Privileged Instruction Exception259
Access Exceptions259
Floating-Point Exception259
Reset259
Non-Maskable Interrupt259
Interrupt259
Unconditional Trap259
Exception Handling Procedure260
Acceptance of Exception Events262
Acceptance Timing and Saved PC Value262
Vector and Site for Saving the Values in the PC and PSW263
Hardware Processing for Accepting and Returning from Exceptions264
Hardware Pre-Processing265
Undefined Instruction Exception265
Privileged Instruction Exception265
Access Exceptions265
Floating-Point Exception265
Reset265
Non-Maskable Interrupt266
Interrupt266
Unconditional Trap266
Return from Exception Handling Routine267
Priority of Exception Events267
Interrupt Controller (Icub)268
Overview268
Register Descriptions270
Interrupt Request Register N (Irn) (N = Interrupt Vector Number)270
Interrupt Request Enable Register M (Ierm) (M = 02H to 1Fh)271
Interrupt Source Priority Register N (Iprn) (N = Interrupt Vector Number)272
Fast Interrupt Set Register (FIR)273
Software Interrupt Generation Register (SWINTR)274
DTC Transfer Request Enable Register N (Dtcern) (N = Interrupt Vector Number)275
DMAC Trigger Select Register M (Dmrsrm) (M = DMAC Channel Number)276
IRQ Control Register I (Irqcri) (I = 0, 1, and 4 to 7)277
IRQ Pin Digital Filter Enable Register 0 (IRQFLTE0)278
IRQ Pin Digital Filter Setting Register 0 (IRQFLTC0)279
Non-Maskable Interrupt Status Register (NMISR)280
Non-Maskable Interrupt Enable Register (NMIER)282
Non-Maskable Interrupt Status Clear Register (NMICLR)284
NMI Pin Interrupt Control Register (NMICR)285
NMI Pin Digital Filter Enable Register (NMIFLTE)285
NMI Pin Digital Filter Setting Register (NMIFLTC)286
Vector Table287
Interrupt Vector Table287
Fast Interrupt Vector Table293
Non-Maskable Interrupt Vector Area293
Interrupt Operation294
Detecting Interrupts294
Operation of Status Flags for Edge-Detected Interrupts294
Operation of Status Flags for Level-Detected Interrupts296
Enabling and Disabling Interrupt Sources297
Selecting Interrupt Request Destinations298
Determining Priority300
Multiple Interrupts300
Fast Interrupt300
Digital Filter301
External Pin Interrupts301
Non-Maskable Interrupt Operation302
Return from Power-Down States303
Return from Sleep Mode or Deep Sleep Mode303
Return from Software Standby Mode303
Usage Note304
Note on WAIT Instruction Used with Non-Maskable Interrupt304
Buses305
Overview305
Description of Buses307
CPU Buses307
Memory Buses307
Internal Main Buses307
Internal Peripheral Buses308
Write Buffer Function (Internal Peripheral Bus)309
Parallel Operation310
Register Descriptions311
Bus Error Status Clear Register (BERCLR)311
Bus Error Monitoring Enable Register (BEREN)311
Bus Error Status Register 1 (BERSR1)312
Bus Error Status Register 2 (BERSR2)312
Bus Priority Control Register (BUSPRI)313
Bus Error Monitoring Section315
Types of Bus Error315
Illegal Address Access315
Timeout315
Operations When a Bus Error Occurs316
Conditions Leading to Bus Errors316
Interrupt317
Interrupt Source317
Memory-Protection Unit (MPU)318
Overview318
Types of Access Control320
Regions for Access Control320
Background Region320
Overlap between Regions320
Instructions and Data that Span Regions320
Register Descriptions321
Region-N Start Page Number Register (Rspagen) (N = 0 to 7)321
Region-N End Page Number Register (Repagen) (N = 0 to 7)322
Memory-Protection Enable Register (MPEN)323
Background Access Control Register (MPBAC)324
Memory-Protection Error Status-Clearing Register (MPECLR)325
Memory-Protection Error Status Register (MPESTS)326
Data Memory-Protection Error Address Register (MPDEA)327
Region Search Address Register (MPSA)327
Region Search Operation Register (MPOPS)328
Region Invalidation Operation Register (MPOPI)328
Instruction-Hit Region Register (MHITI)329
Data-Hit Region Register (MHITD)331
Functions333
Memory Protection333
Region Search333
Protection of Registers Related to the Memory-Protection Unit333
Flow for Determination of Access by the Memory-Protection Function334
Procedures for Using Memory Protection336
Setting Access-Control Information336
Enabling Memory Protection336
Transition to User Mode336
Processing in Response to Memory-Protection Errors336
DMA Controller (DMACA)338
Overview338
Register Descriptions340
DMA Source Address Register (DMSAR)340
DMA Destination Address Register (DMDAR)340
DMA Transfer Count Register (DMCRA)341
DMA Block Transfer Count Register (DMCRB)343
DMA Transfer Mode Register (DMTMD)344
DMA Interrupt Setting Register (DMINT)345
DMA Address Mode Register (DMAMD)347
DMA Offset Register (DMOFR)350
DMA Transfer Enable Register (DMCNT)351
DMA Software Start Register (DMREQ)352
DMA Status Register (DMSTS)353
DMA Activation Source Flag Control Register (DMCSL)355
DMA Module Activation Register (DMAST)356
Operation357
Transfer Mode357
Extended Repeat Area Function361
Address Update Function Using Offset363
Activation Sources367
Operation Timing368
DMAC Execution Cycles369
Activating the DMAC370
Starting DMA Transfer371
Registers During DMA Transfer371
Channel Priority372
Ending DMA Transfer373
Transfer End by Completion of Specified Total Number of Transfer Operations373
Transfer End by Repeat Size End Interrupt373
Transfer End by Interrupt on Extended Repeat Area Overflow374
Interrupts375
Event Link Function376
Low Power Consumption Function377
Usage Notes378
DMA Transfer to Peripheral Modules378
Access to the Registers During DMA Transfer378
DMA Transfer to Reserved Areas378
Interrupt Request by the DMA Activation Source Flag Control Register (DMCSL) at the End of each Transfer378
Setting of DMAC Activation Source Select Register of the Interrupt Controller (Icu.dmrsrm)378
Suspending or Restarting DMA Activation378
Data Transfer Controller (Dtca)379
Overview379
Register Descriptions381
DTC Mode Register a (MRA)381
DTC Mode Register B (MRB)382
DTC Transfer Source Register (SAR)383
DTC Transfer Destination Register (DAR)383
DTC Transfer Count Register a (CRA)384
DTC Transfer Count Register B (CRB)385
DTC Control Register (DTCCR)385
DTC Vector Base Register (DTCVBR)386
DTC Address Mode Register (DTCADMOD)386
DTC Module Start Register (DTCST)387
DTC Status Register (DTCSTS)388
Request Sources389
Allocating Transfer Information and DTC Vector Table389
Operation391
Transfer Information Read Skip Function393
Transfer Information Write-Back Skip Function394
Normal Transfer Mode395
Repeat Transfer Mode396
Block Transfer Mode397
Chain Transfer398
Operation Timing399
Execution Cycles of the DTC402
DTC Bus Mastership Release Timing402
DTC Setting Procedure403
Examples of DTC Usage404
Normal Transfer404
Chain Transfer When the Counter Is 0405
Interrupt Source406
Event Link406
Low Power Consumption Function407
19.10 Usage Notes408
Start Address of Transfer Information408
Allocating Transfer Information408
Setting the DTC Transfer Request Enable Register in the Interrupt Controller (Icu.dtcern)409
Event Link Controller (ELC)410
Overview410
Register Descriptions411
Event Link Control Register (ELCR)411
Event Link Setting Register N (Elsrn) (N = 1 to 4, 7, 8, 10, 12, 14 to 16, 18 to 29)412
Event Link Option Setting Register a (ELOPA)415
Event Link Option Setting Register B (ELOPB)415
Event Link Option Setting Register C (ELOPC)416
Event Link Option Setting Register D (ELOPD)416
Port Group Setting Register N (Pgrn) (N = 1, 2)417
Port Group Control Register N (Pgcn) (N = 1, 2)418
Port Buffer Register N (Pdbfn) (N = 1, 2)419
Event Link Port Setting Register M (Pelm) (M = 0 to 3)420
Event Link Software Event Generation Register (ELSEGR)421
Operation422
Relation between Interrupt Handling and Event Linking422
Event Linkage423
Operation of Peripheral Timer Modules When Event Signal Is Input424
Operation of A/D and D/A Converters When Event Signal Is Input424
I/O Port Operation When Event Signal Is Input and Event Generation424
Example of Procedure for Linking Events428
Usage Notes429
Setting Elsrn Register429
Setting Bit-Rotating Operation of Output Port Groups429
Linking DMA/DTC Transfer End Signal as Event429
Clock Settings429
Module Stop Function Setting429
I/O Ports430
Overview430
I/O Port Configuration432
Register Descriptions441
Port Direction Register (PDR)441
Port Output Data Register (PODR)442
Port Input Data Register (PIDR)443
Port Mode Register (PMR)444
Open Drain Control Register 0 (ODR0)445
Open Drain Control Register 1 (ODR1)446
Pull-Up Control Register (PCR)447
Drive Capacity Control Register (DSCR)448
Initialization of the Port Direction Register (PDR)449
Handling of Unused Pins450
Multi-Function Pin Controller (MPC)451
Overview451
Register Descriptions457
Write-Protect Register (PWPR)457
P0N Pin Function Control Register (P0Npfs) (N = 3, 5, 7)458
P1N Pin Function Control Registers (P1Npfs) (N = 4 to 7)459
P2N Pin Function Control Register (P2Npfs) (N = 1, 2, 5 to 7)460
P3N Pin Function Control Registers (P3Npfs) (N = 0, 1)461
P4N Pin Function Control Registers (P4Npfs) (N = 0 to 7)462
Pbn Pin Function Control Registers (Pbnpfs) (N = 0, 1, 3, 5, 7)463
Pcn Pin Function Control Registers (Pcnpfs) (N = 0, 2 to 7)464
Pdn Pin Function Control Registers (Pdnpfs) (N = 3)465
Pen Pin Function Control Registers (Penpfs) (N = 0 to 4)466
Pjn Pin Function Control Registers (Pjnpfs) (N = 3)468
Usage Notes469
Procedure for Specifying Input/Output Pin Function469
Notes on MPC Register Setting469
Note on Using Analog Functions470
Notes on Using the CTSU Function of the Capacitive Touch Sensing Unit470
Multi-Function Timer Pulse Unit 2 (Mtu2A)471
Overview471
Register Descriptions476
Timer Control Register (TCR)476
Timer Mode Register (TMDR)479
Timer I/O Control Register (TIOR)481
Timer Interrupt Enable Register (TIER)491
Timer Status Register (TSR)493
Timer Buffer Operation Transfer Mode Register (TBTM)494
Timer Input Capture Control Register (TICCR)495
Timer A/D Converter Start Request Control Register (TADCR)496
Timer A/D Converter Start Request Cycle Set Registers a and B (TADCORA and TADCORB)497
Timer A/D Converter Start Request Cycle Set Buffer Registers a and B (TADCOBRA and TADCOBRB)498
Timer Counter (TCNT)498
Timer General Register (TGR)499
Timer Start Registers (TSTR)500
Timer Synchronous Registers (TSYR)501
Timer Read/Write Enable Registers (TRWER)502
Timer Output Master Enable Registers (TOER)503
Timer Output Control Registers 1 (TOCR1)504
Timer Output Control Registers 2 (TOCR2)506
Timer Output Level Buffer Registers (TOLBR)508
Timer Gate Control Registers (TGCR)509
Timer Subcounters (TCNTS)510
Timer Dead Time Data Registers (TDDR)510
Timer Cycle Data Registers (TCDR)511
Timer Cycle Buffer Registers (TCBR)511
Timer Interrupt Skipping Set Registers (TITCR)512
Timer Interrupt Skipping Counters (TITCNT)513
Timer Buffer Transfer Set Registers (TBTER)514
Timer Dead Time Enable Registers (TDER)515
Timer Waveform Control Registers (TWCR)516
Noise Filter Control Registers (NFCR)517
Bus Master Interface518
Operation519
Basic Functions519
Synchronous Operation525
Buffer Operation527
Cascaded Operation531
PWM Modes536
Phase Counting Mode540
Reset-Synchronized PWM Mode546
Complementary PWM Mode549
A/D Converter Start Request Delaying Function580
Noise Filter584
Interrupt Sources585
Interrupt Sources and Priorities585
DTC/DMAC Activation586
A/D Converter Activation586
Operation Timing588
Input/Output Timing588
Interrupt Signal Timing594
Usage Notes596
Module Clock Stop Mode Setting596
Count Clock Restrictions596
Notes on Cycle Setting596
Contention between TCNT Write and Clear Operations597
Contention between TCNT Write and Increment Operations597
Contention between TGR Write Operation and Compare Match598
Contention between Buffer Register Write Operation and Compare Match598
Contention between Buffer Register Write and TCNT Clear Operations599
Contention between TGR Read Operation and Input Capture599
Contention between TGR Write Operation and Input Capture600
Contention between Buffer Register Write Operation and Input Capture600
Contention between MTU2.TCNT Write Operation and Overflow/Underflow in Cascaded Operation601
Counter Value When Count Operation Is Stopped in Complementary PWM Mode602
Buffer Operation Setting in Complementary PWM Mode602
Buffer Operation and Compare Match Flags in Reset-Synchronized PWM Mode603
Overflow Flags in Reset-Synchronized PWM Mode604
Contention between Overflow/Underflow and Counter Clearing605
Contention between TCNT Write Operation and Overflow/Underflow605
Notes on Transition from Normal Mode or PWM Mode 1 to Reset-Synchronized PWM Mode606
Output Level in Complementary PWM Mode or Reset-Synchronized PWM Mode606
Interrupts During Periods in the Module Stop State606
Simultaneous Input Capture in MTU1.TCNT and MTU2.TCNT in Cascade Connection606
Notes When Complementary PWM Mode Output Protection Functions Are Not Used607
Points for Caution to Prevent Malfunctions in Synchronous Clearing for Complementary PWM Mode607
Continuous Output of Interrupt Signal in Response to a Compare Match609
Usage Notes on A/D Converter Delaying Function in Complementary PWM Mode609
MTU Output Pin Initialization611
Operating Modes611
Operation in Case of Re-Setting Due to Error During Operation611
Overview of Pin Initialization Procedures and Mode Transitions in Case of Error During Operation612
Operations Linked by the ELC638
Event Signal Output to the ELC638
MTU Operations in Response to Receiving Event Signals from the ELC638
Notes on MTU by Event Signal Reception from the ELC639
Port Output Enable 2 (Poe2A)640
Overview640
Register Descriptions643
Input Level Control/Status Register 1 (ICSR1)643
Output Level Control/Status Register 1 (OCSR1)645
Input Level Control/Status Register 2 (ICSR2)646
Software Port Output Enable Register (SPOER)647
Port Output Enable Control Register 1 (POECR1)648
Port Output Enable Control Register 2 (POECR2)649
Input Level Control/Status Register 3 (ICSR3)650
Operation651
Input Level Detection Operation653
Output-Level Compare Operation654
High-Impedance Control Using Registers655
High-Impedance Control on Detection of Stopped Oscillation655
High-Impedance Control in Response to Receiving an Event Signal from the ELC655
Release from the High-Impedance655
Interrupts656
Usage Notes656
Transitions to Software Standby Mode656
When the POE Is Not Used656
Specifying Pins Corresponding to the MTU656
Notes on High-Impedance Control by Event Signal Reception from the ELC656
Overview657
Register Descriptions661
Timer Control Register (TCR)661
Timer Mode Register (TMDR)665
Timer I/O Control Register (TIORH, TIORL, TIOR)666
Timer Interrupt Enable Register (TIER)674
Timer Status Register (TSR)675
Timer Counter (TCNT)678
Timer General Register a (TGRA), Timer General Register B (TGRB), Timer General Register C (TGRC), Timer General Register D (TGRD)678
Timer Start Register (TSTR)679
Timer Synchronous Register (TSYR)680
Noise Filter Control Register (NFCR)681
Operation683
Basic Functions683
Synchronous Operation689
Buffer Operation691
Cascaded Operation694
PWM Modes696
Phase Counting Mode701
Phase Counting Mode Application Example706
Noise Filters707
Interrupt Sources708
DTC Activation709
DMAC Activation709
A/D Converter Activation709
Operation Timing710
Input/Output Timing710
Interrupt Signal Timing714
Usage Notes716
Module Stop Function Setting716
Input Clock Restrictions716
Notes on Cycle Setting716
Conflict between Tpum.tcnt Write and Clear Operations717
Conflict between Tpum.tcnt Write and Increment Operations717
Conflict between Tpum.tgry Write and Compare Match718
Conflict between Buffer Register Write and Compare Match718
Conflict between Tpum.tgry Read and Input Capture719
Conflict between Tpum.tgry Write and Input Capture719
Conflict between Buffer Register Write and Input Capture720
TCNT Simultaneous Input Capture in Cascade Operation720
Conflict between Overflow/Underflow and Counter Clearing721
Conflict between Tpum.tcnt Write and Overflow/Underflow722
Multiplexing of I/O Pins722
Continuous Output of Compare-Match Pulse Interrupt Signal723
Continuous Output of Input-Capture Pulse Interrupt Signal724
Continuous Output of Underflow Pulse Interrupt Signal725
Bit Timer (TMR)726
Overview726
Register Descriptions731
Timer Counter (TCNT)731
Time Constant Register a (TCORA)732
Time Constant Register B (TCORB)732
Timer Control Register (TCR)733
Timer Counter Control Register (TCCR)734
Timer Control/Status Register (TCSR)736
Timer Counter Start Register (TCSTR)738
Operation739
Pulse Output739
External Counter Reset Input740
Operation Timing741
TCNT Count Timing741
Timing of Interrupt Signal Output on a Compare Match742
Timing of Timer Output Signal at Compare Match742
Timing of Counter Clear by Compare Match743
Timing of the External Reset for TCNT743
Timing of Interrupt Signal Output on an Overflow744
Operation with Cascaded Connection745
16-Bit Count Mode745
Compare Match Count Mode745
Interrupt Sources746
Interrupt Sources and DTC Activation746
Link Operation by ELC747
Event Signal Output to ELC747
TMR Operation When Receiving an Event Signal from ELC747
Notes on Operating TMR According to an Event Signal from ELC748
Usage Notes749
Module Stop State Setting749
Notes on Setting Cycle749
Conflict between TCNT Write and Counter Clear749
Conflict between TCNT Write and Increment750
Conflict between TCORA or TCORB Write and Compare Match750
Conflict between Compare Matches a and B751
Switching of Internal Clocks and TCNT Operation751
Clock Source Setting with Cascaded Connection753
Continuous Output of Compare Match Interrupt Signal753
Compare Match Timer (CMT)754
Overview754
Register Descriptions755
Compare Match Timer Start Register 0 (CMSTR0)755
Compare Match Timer Start Register 1 (CMSTR1)755
Compare Match Timer Control Register (CMCR)756
Compare Match Counter (CMCNT)757
Compare Match Constant Register (CMCOR)757
Operation758
Periodic Count Operation758
CMCNT Count Timing758
Interrupts759
Interrupt Sources759
Timing of Compare Match Interrupt Generation759
Link Operations by ELC760
Event Signal Output to ELC760
CMT Operation When Receiving an Event Signal from ELC760
Notes on Operating CMT According to an Event Signal from ELC760
Usage Notes761
Setting the Module Stop Function761
Conflict between CMCNT Counter Writing and Compare Match761
Conflict between CMCNT Counter Writing and Incrementing761
Realtime Clock (Rtce)762
Overview762
Register Descriptions764
64-Hz Counter (R64CNT)764
Second Counter (Rseccnt)/Binary Counter 0 (BCNT0)765
Minute Counter (Rmincnt)/Binary Counter 1 (BCNT1)766
Hour Counter (Rhrcnt)/Binary Counter 2 (BCNT2)767
Day-Of-Week Counter (Rwkcnt)/Binary Counter 3 (BCNT3)768
Date Counter (RDAYCNT)769
Month Counter (RMONCNT)770
Year Counter (RYRCNT)771
Second Alarm Register (Rsecar)/Binary Counter 0 Alarm Register (BCNT0AR)772
Minute Alarm Register (Rminar)/Binary Counter 1 Alarm Register (BCNT1AR)773
Hour Alarm Register (Rhrar)/Binary Counter 2 Alarm Register (BCNT2AR)774
Day-Of-Week Alarm Register (Rwkar)/Binary Counter 3 Alarm Register (BCNT3AR)775
Date Alarm Register (Rdayar)/Binary Counter 0 Alarm Enable Register (BCNT0AER)776
Month Alarm Register (Rmonar)/Binary Counter 1 Alarm Enable Register (BCNT1AER)777
Year Alarm Register (Ryrar)/Binary Counter 2 Alarm Enable Register (BCNT2AER)778
Year Alarm Enable Register (Ryraren)/Binary Counter 3 Alarm Enable Register (BCNT3AER)779
RTC Control Register 1 (RCR1)780
RTC Control Register 2 (RCR2)781
RTC Control Register 3 (RCR3)783
Notes on Using a Low CL Crystal Unit783
Time Error Adjustment Register (RADJ)784
Time Capture Control Register N (Rtccrn) (N = 0, 1)785
Second Capture Register N (Rseccpn) (N = 0, 1)/BCNT0 Capture Register N (Bcnt0Cpn) (N = 0, 1)787
Minute Capture Register N (Rmincpn) (N = 0, 1)/BCNT1 Capture Register N (Bcnt1Cpn) (N = 0, 1)788
Hour Capture Register N (Rhrcpn) (N = 0, 1)/BCNT2 Capture Register N (Bcnt2Cpn) (N = 0, 1)789
Date Capture Register N (Rdaycpn) (N = 0, 1)/BCNT3 Capture Register N (Bcnt3Cpn) (N = 0, 1)790
Month Capture Register N (Rmoncpn) (N = 0, 1)791
Operation792
Outline of Initial Settings of Registers after Power on792
Clock and Count Mode Setting Procedure793
Setting the Time794
30-Second Adjustment794
Reading 64-Hz Counter and Time795
Alarm Function796
Procedure for Disabling Alarm Interrupt797
Time Error Adjustment Function797
Automatic Adjustment797
Adjustment by Software798
Procedure for Changing the Mode of Adjustment799
Procedure for Stopping Adjustment799
Capturing the Time800
Interrupt Sources801
Event Link Output803
Interrupt Handling and Event Linking803
Usage Notes804
Register Writing During Counting804
Use of Periodic Interrupts804
RTCOUT (1-Hz/64-Hz) Clock Output804
Transitions to Low Power Consumption Modes after Setting Registers805
Notes When Writing to and Reading from Registers805
Changing the Count Mode805
Initialization Procedure When the Realtime Clock Is Not to be Used806
Low-Power Timer (LPT)807
Overview807
Register Descriptions808
Low-Power Timer Control Register 1 (LPTCR1)808
Low-Power Timer Control Register 2 (LPTCR2)810
Low-Power Timer Control Register 3 (LPTCR3)811
Low-Power Timer Period Setting Register (LPTPRD)812
Low-Power Timer Compare Register 0 (LPCMR0)814
Low-Power Timer Standby Wakeup Enable Register (LPWUCR)815
Operation816
Periodic Counting Operation816
Count Timing of Low-Power Timer Counter818
Clearing Timing of Low-Power Timer Counter818
Wakeup from Software Standby Mode by an Interrupt through the Event Link Controller (ELC)819
Usage Notes819
Notes on Transition to Software Standby Mode819
Watchdog Timer (WDTA)820
Overview820
Register Descriptions821
WDT Refresh Register (WDTRR)821
WDT Control Register (WDTCR)822
WDT Status Register (WDTSR)825
WDT Reset Control Register (WDTRCR)826
Option Function Select Register 0 (OFS0)826
Operation827
Count Operation in each Start Mode827
Register Start Mode827
Auto-Start Mode829
Control over Writing to the WDTCR and WDTRCR Registers831
Refresh Operation831
Reset Output832
Interrupt Source832
Reading the Down-Counter Value833
Correspondence between Option Function Select Register 0 (OFS0) and WDT Registers833
Independent Watchdog Timer (Iwdta)834
Overview834
Register Descriptions836
IWDT Refresh Register (IWDTRR)836
IWDT Control Register (IWDTCR)837
IWDT Status Register (IWDTSR)840
IWDT Reset Control Register (IWDTRCR)841
IWDT Count Stop Control Register (IWDTCSTPR)842
Option Function Select Register 0 (OFS0)842
Operation843
Count Operation in each Start Mode843
Register Start Mode843
Auto-Start Mode845
Control over Writing to the IWDTCR, IWDTRCR, and IWDTCSTPR Registers847
Refresh Operation848
Status Flags850
Reset Output850
Interrupt Sources850
Reading the Counter Value851
Correspondence between Option Function Select Register 0 (OFS0) and IWDT Registers852
Link Operation by ELC852
Usage Notes852
Refresh Operations852
Clock Divide Ratio Setting852
USB 2.0 Host/Function Module (Usbc)853
Overview853
Register Descriptions855
System Configuration Control Register (SYSCFG)855
System Configuration Status Register 0 (SYSSTS0)857
Device State Control Register 0 (DVSTCTR0)858
CFIFO Port Register (CFIFO) D0FIFO Port Register (D0FIFO) D1FIFO Port Register (D1FIFO)861
CFIFO Port Select Register (CFIFOSEL) D0FIFO Port Select Register (D0FIFOSEL) D1FIFO Port Select Register (D1FIFOSEL)863
CFIFO Port Control Register (CFIFOCTR) D0FIFO Port Control Register (D0FIFOCTR) D1FIFO Port Control Register (D1FIFOCTR)867
Interrupt Enable Register 0 (INTENB0)869
Interrupt Enable Register 1 (INTENB1)870
BRDY Interrupt Enable Register (BRDYENB)871
NRDY Interrupt Enable Register (NRDYENB)872
BEMP Interrupt Enable Register (BEMPENB)873
SOF Output Configuration Register (SOFCFG)874
Interrupt Status Register 0 (INTSTS0)875
Interrupt Status Register 1 (INTSTS1)878
BRDY Interrupt Status Register (BRDYSTS)881
NRDY Interrupt Status Register (NRDYSTS)882
BEMP Interrupt Status Register (BEMPSTS)883
Frame Number Register (FRMNUM)884
USB Request Type Register (USBREQ)885
USB Request Value Register (USBVAL)886
USB Request Index Register (USBINDX)886
USB Request Length Register (USBLENG)887
DCP Configuration Register (DCPCFG)888
DCP Maximum Packet Size Register (DCPMAXP)889
DCP Control Register (DCPCTR)890
Pipe Window Select Register (PIPESEL)893
Pipe Configuration Register (PIPECFG)894
Pipe Maximum Packet Size Register (PIPEMAXP)896
Pipe Cycle Control Register (PIPEPERI)897
Pipen Control Registers (Pipenctr) (N = 1 to 9)898
Pipen Transaction Counter Enable Register (Pipentre) (N = 1 to 5)906
Pipen Transaction Counter Register (Pipentrn) (N = 1 to 5)907
Device Address N Configuration Register (Devaddn) (N = 0 to 5)908
USB Module Control Register (USBMC)909
BC Control Register 0 (USBBCCTRL0)910
Operation912
System Control912
Setting Data to the USB Related Register912
Controller Function Selection912
Controlling USB Data Bus Resistors912
Example of USB External Connection Circuit913
Interrupt Sources920
Interrupt Descriptions922
BRDY Interrupt922
NRDY Interrupt926
BEMP Interrupt929
Device State Transition Interrupt930
Control Transfer Stage Transition Interrupt931
Frame Update Interrupt932
VBUS Interrupt932
Resume Interrupt932
OVRCR Interrupt932
BCHG Interrupt932
DTCH Interrupt932
SACK Interrupt933
SIGN Interrupt933
ATTCH Interrupt933
EOFERR Interrupt933
Portable Device Detection Interrupt933
Pipe Control934
Pipe Control Register Switching Procedures935
Transfer Types935
Endpoint Number935
Maximum Packet Size Setting936
Transaction Counter (for PIPE1 to PIPE5 in Reading Direction)936
Response PID937
Data PID Sequence Bit938
Response PID = NAK Function938
Auto Response Mode938
OUT-NAK Mode938
Null Auto Response Mode939
FIFO Buffer Memory939
FIFO Buffer Clearing940
FIFO Port Functions941
DMA Transfers (D0FIFO and D1FIFO Ports)942
Control Transfers Using DCP943
Control Transfers When the Host Controller Is Selected943
Control Transfers When the Function Controller Is Selected944
Bulk Transfers (PIPE1 to PIPE5)945
Interrupt Transfers (PIPE6 to PIPE9)945
Interval Counter During Interrupt Transfers When the Host Controller Is Selected945
Isochronous Transfers (PIPE1 and PIPE2)946
Error Detection in Isochronous Transfers946
Data PID947
Interval Counter947
SOF Interpolation Function954
Pipe Schedule955
Conditions for Generating a Transaction955
Transfer Schedule955
Enabling USB Communication955
Usage Notes956
Setting the Module Stop Function956
Battery Charging Detection Processing957
Processing When Function Controller Is Selected957
Processing When Host Controller Is Selected959
Serial Communications Interface (Scig, Scih)962
Overview962
Register Descriptions970
Receive Shift Register (RSR)970
Receive Data Register (RDR)970
Receive Data Register H, L, HL (RDRH, RDRL, RDRHL)971
Transmit Data Register (TDR)971
Transmit Data Register H, L, HL (TDRH, TDRL, TDRHL)972
Transmit Shift Register (TSR)972
Serial Mode Register (SMR)973
Serial Control Register (SCR)977
Serial Status Register (SSR)981
Smart Card Mode Register (SCMR)986
Bit Rate Register (BRR)988
Modulation Duty Register (MDDR)996
Serial Extended Mode Register (SEMR)997
Noise Filter Setting Register (SNFR)1000
C Mode Register 1 (SIMR1)1001
I 2 C Mode Register 2 (SIMR2)1002
I 2 C Mode Register 3 (SIMR3)1003
C Status Register (SISR)1005
SPI Mode Register (SPMR)1006
Extended Serial Module Enable Register (ESMER)1007
Control Register 0 (CR0)1008
Control Register 1 (CR1)1008
Control Register 2 (CR2)1009
Control Register 3 (CR3)1010
Port Control Register (PCR)1010
Interrupt Control Register (ICR)1011
Status Register (STR)1012
Status Clear Register (STCR)1013
Control Field 0 Data Register (CF0DR)1013
Control Field 0 Compare Enable Register (CF0CR)1014
Control Field 0 Receive Data Register (CF0RR)1014
Primary Control Field 1 Data Register (PCF1DR)1014
Secondary Control Field 1 Data Register (SCF1DR)1015
Control Field 1 Compare Enable Register (CF1CR)1015
Control Field 1 Receive Data Register (CF1RR)1015
Timer Control Register (TCR)1016
Timer Mode Register (TMR)1016
Timer Prescaler Register (TPRE)1017
Timer Count Register (TCNT)1017
Operation in Asynchronous Mode1018
Serial Data Transfer Format1018
Receive Data Sampling Timing and Reception Margin in Asynchronous Mode1020
Clock1021
Double-Speed Mode1021
CTS and RTS Functions1022
SCI Initialization (Asynchronous Mode)1023
Serial Data Transmission (Asynchronous Mode)1025
Serial Data Reception (Asynchronous Mode)1029
Multi-Processor Communications Function1033
Multi-Processor Serial Data Transmission1034
Multi-Processor Serial Data Reception1035
Operation in Clock Synchronous Mode1038
Clock1038
CTS and RTS Functions1039
SCI Initialization (Clock Synchronous Mode)1040
Serial Data Transmission (Clock Synchronous Mode)1041
Serial Data Reception (Clock Synchronous Mode)1045
Simultaneous Serial Data Transmission and Reception (Clock Synchronous Mode)1048
Operation in Smart Card Interface Mode1049
Sample Connection1049
Data Format (Except in Block Transfer Mode)1050
Block Transfer Mode1051
Receive Data Sampling Timing and Reception Margin1052
SCI Initialization (Smart Card Interface Mode)1053
Serial Data Transmission (Except in Block Transfer Mode)1055
Serial Data Reception (Except in Block Transfer Mode)1058
Clock Output Control1060
Operation in Simple I C Mode1061
Generation of Start, Restart, and Stop Conditions1062
Clock Synchronization1064
SSDA Output Delay1065
SCI Initialization (Simple I 2 C Mode)1066
Operation in Master Transmission (Simple I 2 C Mode)1067
Master Reception (Simple I 2 C Mode)1069
Recovery from Bus Hang-Up1071
Operation in Simple SPI Mode1072
States of Pins in Master and Slave Modes1073
SS Function in Master Mode1073
SS Function in Slave Mode1073
Relationship between Clock and Transmit/Receive Data1074
SCI Initialization (Simple SPI Mode)1075
Transmission and Reception of Serial Data (Simple SPI Mode)1075
Bit Rate Modulation Function1075
33.10 Extended Serial Mode Control Section: Description of Operation1076
Serial Transfer Protocol1076
Transmitting a Start Frame1077
Receiving a Start Frame1080
Priority Interrupt Bit1085
Detection of Bus Collisions1086
Digital Filter for Input on the RXDX12 Pin1087
Bit Rate Measurement1088
Selectable Timing for Sampling Data Received through RXDX121089
Timer1090
33.11 Noise Cancellation Function1092
33.12 Interrupt Sources1093
Buffer Operations for TXI and RXI Interrupts1093
Interrupts in Asynchronous Mode, Clock Synchronous Mode, and Simple SPI Mode1093
Interrupts in Smart Card Interface Mode1094
Interrupts in Simple I C Mode1095
Interrupt Requests from the Extended Serial Mode Control Section1096
33.13 Event Linking1097
33.14 Usage Notes1098
Setting the Module Stop Function1098
Break Detection and Processing1098
Mark State and Sending Breaks1098
Receive Error Flags and Transmit Operations (Clock Synchronous Mode and Simple SPI Mode)1098
Writing Data to the TDR Register1098
Restrictions on Clock Synchronous Transmission (Clock Synchronous Mode and Simple SPI Mode)1099
Restrictions on Using DMAC or DTC1100
Notes on Starting Transfer1100
SCI Operations During Low Power Consumption State1100
External Clock Input in Clock Synchronous Mode and Simple SPI Mode1103
Limitations on Simple SPI Mode1104
Limitation 1 on Usage of the Extended Serial Mode Control Section1105
Limitation 2 on Usage of the Extended Serial Mode Control Section1105
Note on Transmit Enable Bit (te Bit)1106
Note on Stopping Reception When Using the RTS Function in Asynchronous Mode1106
Irda Interface1107
Overview1107
Register Descriptions1108
Irda Control Register (IRCR)1108
Operation1110
Transmission1110
Reception1111
Selecting High-Level Pulse Width1111
Usage Notes1112
Module Stop Function Setting1112
SCI5 Setting1112
Minimum Pulse-Width During Reception1112
Notes on Irda Initial Setting/Resetting1112
I 2 C-Bus Interface (Riica)1113
Overview1113
Register Descriptions1116
I 2 C-Bus Control Register 1 (ICCR1)1116
I 2 C-Bus Control Register 2 (ICCR2)1118
I 2 C-Bus Mode Register 1 (ICMR1)1122
C-Bus Mode Register 2 (ICMR2)1123
I 2 C-Bus Mode Register 3 (ICMR3)1125
I 2 C-Bus Function Enable Register (ICFER)1127
I 2 C-Bus Status Enable Register (ICSER)1129
C-Bus Interrupt Enable Register (ICIER)1131
I 2 C-Bus Status Register 1 (ICSR1)1133
I 2 C-Bus Status Register 2 (ICSR2)1136
Slave Address Register Ly (Sarly) (y = 0 to 2)1139
Slave Address Register Uy (Saruy) (y = 0 to 2)1140
I 2 C-Bus Bit Rate Low-Level Register (ICBRL)1141
I 2 C-Bus Bit Rate High-Level Register (ICBRH)1142
I 2 C-Bus Transmit Data Register (ICDRT)1144
I 2 C-Bus Receive Data Register (ICDRR)1144
I 2 C-Bus Shift Register (ICDRS)1144
Operation1145
Communication Data Format1145
Initial Settings1146
Master Transmit Operation1147
Master Receive Operation1150
Slave Transmit Operation1156
Slave Receive Operation1159
SCL Synchronization Circuit1161
SDA Output Delay Function1162
Digital Noise Filter Circuit1163
Address Match Detection1164
Slave-Address Match Detection1164
Detection of the General Call Address1166
Device-ID Address Detection1167
Host Address Detection1169
Automatic Low-Hold Function for SCL1170
Function to Prevent Wrong Transmission of Transmit Data1170
NACK Reception Transfer Abort Function1171
Function to Prevent Failure to Receive Data1172
Arbitration-Lost Detection Functions1174
Master Arbitration-Lost Detection (MALE Bit)1174
Function to Detect Loss of Arbitration During NACK Transmission (NALE Bit)1176
Slave Arbitration-Lost Detection (SALE Bit)1177
35.10 Start Condition/Restart Condition/Stop Condition Issuing Function1178
Issuing a Start Condition1178
Issuing a Restart Condition1178
Issuing a Stop Condition1179
35.11 Bus Hanging1180
Timeout Function1180
Extra SCL Clock Cycle Output Function1182
RIIC Reset and Internal Reset1183
35.12 Smbus Operation1184
Smbus Timeout Measurement1184
Packet Error Code (PEC)1185
Smbus Host Notification Protocol (Notify ARP Master Command)1185
35.13 Interrupt Sources1186
Buffer Operation for TXI and RXI Interrupts1186
Initialization of Registers and Functions When a Reset Is Issued or a Condition Is Detected1187
Event Link Function (Output)1188
Interrupt Handling and Event Linking1188
35.16 Usage Notes1189
Setting Module Stop Function1189
Notes on Starting Transfer1189
CAN Module (RSCAN)1190
Overview1190
Register Descriptions1193
Bit Configuration Register L (CFGL)1193
Bit Configuration Register H (CFGH)1194
Control Register L (CTRL)1195
Control Register H (CTRH)1197
Status Register L (STSL)1199
Status Register H (STSH)1200
Error Flag Register L (ERFLL)1201
Error Flag Register H (ERFLH)1203
Global Configuration Register L (GCFGL)1204
Global Configuration Register H (GCFGH)1205
Global Control Register L (GCTRL)1206
Global Control Register H (GCTRH)1207
Global Status Register (GSTS)1207
Global Error Flag Register (GERFLL)1208
Global Transmit Interrupt Status Register (GTINTSTS)1209
Timestamp Register (GTSC)1210
Receive Rule Number Configuration Register (GAFLCFG)1210
Receive Rule Entry Register Jal (Gaflidlj) (J = 0 to 15)1211
Receive Rule Entry Register Jah (Gaflidhj) (J = 0 to 15)1212
Receive Rule Entry Register Jbl (Gaflmlj) (J = 0 to 15)1213
Receive Rule Entry Register Jbh (Gaflmhj) (J = 0 to 15)1214
Receive Rule Entry Register Jcl (Gaflplj) (J = 0 to 15)1215
Receive Rule Entry Register Jch (Gaflphj) (J = 0 to 15)1216
Receive Buffer Number Configuration Register (RMNB)1217
Receive Buffer Receive Complete Flag Register (RMND0)1217
Receive Buffer Register Nal (Rmidln) (N = 0 to 15)1218
Receive Buffer Register Nah (Rmidhn) (N = 0 to 15)1219
Receive Buffer Register Nbl (Rmtsn) (N = 0 to 15)1220
Receive Buffer Register Nbh (Rmptrn) (N = 0 to 15)1221
Receive Buffer Register Ncl (Rmdf0N) (N = 0 to 15)1222
Receive Buffer Register Nch (Rmdf1N) (N = 0 to 15)1222
Receive Buffer Register Ndl (Rmdf2N) (N = 0 to 15)1223
Receive Buffer Register Ndh (Rmdf3N) (N = 0 to 15)1223
Receive FIFO Control Register M (Rfccm) (M = 0, 1)1224
Receive FIFO Status Register M (Rfstsm) (M = 0, 1)1225
Receive FIFO Pointer Control Register M (Rfpctrm) (M = 0, 1)1226
Receive FIFO Access Register Mal (Rfidlm) (M = 0, 1)1227
Receive FIFO Access Register Mah (Rfidhm) (M = 0, 1)1227
Receive FIFO Access Register Mbl (Rftsm) (M = 0, 1)1228
Receive FIFO Access Register Mbh (Rfptrm) (M = 0, 1)1228
Receive FIFO Access Register Mcl (Rfdf0M) (M = 0, 1)1229
Receive FIFO Access Register Mch (Rfdf1M) (M = 0, 1)1229
Receive FIFO Access Register Mdl (Rfdf2M) (M = 0, 1)1230
Receive FIFO Access Register Mdh (Rfdf3M) (M = 0, 1)1230
Transmit/Receive FIFO Control Register 0L (CFCCL0)1231
Transmit/Receive FIFO Control Register 0H (CFCCH0)1233
Transmit/Receive FIFO Status Register 0 (CFSTS0)1234
Transmit/Receive FIFO Pointer Control Register 0 (CFPCTR0)1236
Transmit/Receive FIFO Access Register 0AL (CFIDL0)1237
Transmit/Receive FIFO Access Register 0AH (CFIDH0)1238
Transmit/Receive FIFO Access Register 0BL (CFTS0)1239
Transmit/Receive FIFO Access Register 0BH (CFPTR0)1240
Transmit/Receive FIFO Access Register 0CL (CFDF00)1241
Transmit/Receive FIFO Access Register 0CH (CFDF10)1241
Transmit/Receive FIFO Access Register 0DL (CFDF20)1242
Transmit/Receive FIFO Access Register 0DH (CFDF30)1242
Receive FIFO Message Lost Status Register (RFMSTS)1243
Transmit/Receive FIFO Message Lost Status Register (CFMSTS)1243
Receive FIFO Interrupt Status Register (RFISTS)1244
Transmit/Receive FIFO Receive Interrupt Status Register (CFISTS)1244
Transmit Buffer Control Register P (Tmcp) (P = 0 to 3)1245
Transmit Buffer Status Register P (Tmstsp) (P = 0 to 3)1246
Transmit Buffer Transmit Request Status Register (TMTRSTS)1247
Transmit Buffer Transmit Complete Status Register (TMTCSTS)1248
Transmit Buffer Transmit Abort Status Register (TMTASTS)1249
Transmit Buffer Interrupt Enable Register (TMIEC)1250
Transmit Buffer Register Pal (Tmidlp) (P = 0 to 3)1250
Transmit Buffer Register Pah (Tmidhp) (P = 0 to 3)1251
Transmit Buffer Register Pbh (Tmptrp) (P = 0 to 3)1252
Transmit Buffer Register Pcl (Tmdf0P) (P = 0 to 3)1253
Transmit Buffer Register Pch (Tmdf1P) (P = 0 to 3)1253
Transmit Buffer Register Pdl (Tmdf2P) (P = 0 to 3)1254
Transmit Buffer Register Pdh (Tmdf3P) (P = 0 to 3)1254
Transmit History Buffer Control Register (THLCC0)1255
Transmit History Buffer Status Register (THLSTS0)1256
Transmit History Buffer Access Register (THLACC0)1257
Transmit History Buffer Pointer Control Register (THLPCTR0)1258
Global RAM Window Control Register (GRWCR)1259
Global Test Configuration Register (GTSTCFG)1260
Global Test Control Register (GTSTCTRL)1260
Global Test Protection Unlock Register (GLOCKK)1261
RAM Test Register R (Rpgaccr) (R = 0 to 127)1261
CAN Modes1262
Global Modes1262
Channel Modes1264
Reception Function1268
Data Processing Using the Receive Rule Table1268
Timestamp1270
Transmission Functions1271
Transmit Priority Determination1271
Transmission Using Transmit Buffers1272
Transmission Using FIFO Buffers1272
Transmit History Function1275
Test Function1276
Standard Test Mode1276
Listen-Only Mode1276
Self-Test Mode (Loopback Mode)1277
RAM Test1277
Interrupt1278
RAM Window1281
Initial Settings1282
Clock Setting1283
Bit Timing Setting1283
Communication Speed Setting1284
Receive Rule Setting1285
Buffer Setting1286
36.10 Reception Procedure1287
Receive Buffer Reading Procedure1287
FIFO Buffer Reading Procedure1289
36.11 Transmission Procedure1291
Procedure for Transmission from Transmit Buffers1291
Procedure for Transmission from Transmit/Receive FIFO Buffers1294
Transmit History Buffer Reading Procedure1297
36.12 Test Settings1298
Self-Test Mode Setting Procedure1298
Protection Unlock Procedure1299
RAM Test Setting Procedure1300
36.13 Notes on the CAN Module1301
Serial Sound Interface (SSI)1302
Overview1302
Register Descriptions1304
Control Register (SSICR)1304
Status Register (SSISR)1308
FIFO Control Register (SSIFCR)1310
FIFO Status Register (SSIFSR)1312
Transmit FIFO Data Register (SSIFTDR)1314
Receive FIFO Data Register (SSIFRDR)1314
TDM Mode Register (SSITDMR)1315
Operation1316
Bus Format1316
Non-Compressed Mode1316
WS Continue Mode1322
Operating States1323
Transmit Operation1324
Receive Operation1327
Serial Bit Clock Control1329
Interrupt Sources1329
Usage Notes1330
Setting the Module Stop Function1330
Notes on Changing Transmission Modes1330
Limits on WS Continue Mode1330
Serial Peripheral Interface (Rspia)1331
Overview1331
Register Descriptions1335
RSPI Control Register (SPCR)1335
RSPI Slave Select Polarity Register (SSLP)1337
RSPI Pin Control Register (SPPCR)1338
RSPI Status Register (SPSR)1339
RSPI Data Register (SPDR)1342
RSPI Sequence Control Register (SPSCR)1345
RSPI Sequence Status Register (SPSSR)1346
RSPI Bit Rate Register (SPBR)1347
RSPI Data Control Register (SPDCR)1348
RSPI Clock Delay Register (SPCKD)1350
RSPI Slave Select Negation Delay Register (SSLND)1351
RSPI Next-Access Delay Register (SPND)1352
RSPI Control Register 2 (SPCR2)1353
RSPI Command Register M (Spcmdm) (M = 0 to 7)1355
Operation1358
Overview of RSPI Operations1358
Controlling RSPI Pins1359
RSPI System Configuration Examples1360
Single Master/Single Slave (with this MCU Acting as Master)1360
Single Master/Single Slave (with this MCU Acting as Slave)1361
Single Master/Multi-Slave (with this MCU Acting as Master)1362
Single Master/Multi-Slave (with this MCU Acting as Slave)1363
Multi-Master/Multi-Slave (with this MCU Acting as Master)1364
Master (Clock Synchronous Operation)/Slave (Clock Synchronous Operation) (with this MCU Acting as Master)1365
Master (Clock Synchronous Operation)/Slave (Clock Synchronous Operation) (with this MCU Acting as Slave)1365
Data Format1366
When Parity Is Disabled (SPCR2.SPPE = 0)1367
When Parity Is Enabled (SPCR2.SPPE = 1)1371
Transfer Format1375
Cpha = 01375
Cpha = 11376
Communications Operating Mode1377
Full-Duplex Synchronous Serial Communications (SPCR.TXMD = 0)1377
Transmit Operations Only (SPCR.TXMD = 1)1378
Transmit Buffer Empty/Receive Buffer Full Interrupts1379
Error Detection1381
Overrun Error1382
Parity Error1384
Mode Fault Error1385
Initializing RSPI1386
Initialization by Clearing the SPE Bit1386
System Reset1386
SPI Operation1387
Master Mode Operation1387
Slave Mode Operation1397
Clock Synchronous Operation1401
Master Mode Operation1401
Slave Mode Operation1405
Loopback Mode1407
Self-Diagnosis of Parity Bit Function1408
Interrupt Sources1409
Link Operation by Event Linking1410
Receive Buffer Full Event Output1410
Transmit Buffer Empty Event Output1410
Mode Fault, Overrun, or Parity Error Event Output1410
RSPI Idle Event Output1411
Transmission-Completed Event Output1411
Usage Notes1412
Setting Module Stop Function1412
Note on Low Power Consumption Functions1412
Notes on Starting Transfer1412
Notes on the SPRF and SPTEF Flags1412
CRC Calculator (CRC)1413
Overview1413
Register Descriptions1414
CRC Control Register (CRCCR)1414
CRC Data Input Register (CRCDIR)1414
CRC Data Output Register (CRCDOR)1415
Operation1416
Usage Notes1419
Module Stop Function Setting1419
Note on Transmission1419
SD Host Interface (Sdhia)1420
Overview1420
Register Details1421
Command Register (SDCMD)1421
Argument Register (SDARG)1423
Data Stop Register (SDSTOP)1423
Block Count Register (SDBLKCNT)1424
Response Register 10 (SDRSP10), Response Register 32 (SDRSP32), Response Register 54 (SDRSP54), Response Register 76 (SDRSP76)1425
SD Status Register 1 (SDSTS1)1426
SD Status Register 2 (SDSTS2)1429
SD Interrupt Mask Register 1 (SDIMSK1)1433
SD Interrupt Mask Register 2 (SDIMSK2)1434
SDHI Clock Control Register (SDCLKCR)1435
Transfer Data Size Register (SDSIZE)1436
Card Access Option Register (SDOPT)1437
SD Error Status Register 1 (SDERSTS1)1438
SD Error Status Register 2 (SDERSTS2)1439
SD Buffer Register (SDBUFR)1440
SDIO Mode Control Register (SDIOMD)1440
SDIO Status Register (SDIOSTS)1442
SDIO Interrupt Mask Register (SDIOIMSK)1443
DMA Transfer Enable Register (SDDMAEN)1444
SDHI Software Reset Register (SDRST)1445
Swap Control Register (SDSWAP)1446
SDHI Operation1447
Data Block Format of the SD Card1447
SD Buffer and the SDBUFR Register1448
SD Card Detection1449
Using the SDHI_CD Pin to Detect an SD Card1449
Using the SDHI_D3 Pin to Detect an SD Card1449
SD Card Write Protection1450
Using the SDHI_WP Pin to Enable Write Protection1450
Using a Command to Enable Write Protection1450
Communication Errors and Timeouts1451
Examples of Issuing a Command1452
Command Absent of Response Reception and Data Transfer1452
Command Absent of Data Transfer1453
Single Block Read Command (CMD17)1454
Single Block Write Command (CMD24)1456
Multi-Block Read Command (CMD18)1458
Multi-Block Write Command (CMD25)1460
IO_RW_DIRECT Command (CMD52)1462
IO_RW_EXTENDED Command (CMD53 (Multi-Block Read))1463
IO_RW_EXTENDED (CMD53 Multi-Block Write)1465
DMA Transfer1467
Interrupts1469
DMA Transfer Triggered by Interrupt Requests1470
Notes on Using the SDHI1471
Illegal Read Access During a Multi-Block Read and How to Avoid It1471
SDBUFR Register Illegal Write Error1471
Automatic Control of the SDHI Clock Output1472
Restrictions on Setting the C52PUB Bit During a Multi-Block Write Sequence1472
Note on Setting the SDCLKCR Register1472
Writing to the SDSTOP Register During a Multi-Block Read Sequence1472
Controlling Module Operation1472
Bluetooth Low Energy (BLE)1473
Overview1473
Operation1476
State Transitions1476
Interrupts1477
Usage Notes1478
RF Transceiver Power-Supply1478
Wireless Standards1479
Notes on Board Design1479
Trusted Secure IP (TSIP-Lite)1480
Overview1480
Operation1482
Operating Modes and State Transitions1482
Encryption Engine1483
Key Installation1484
Encryption and Decryption1485
Generating Key Generation Information (by Using Random Numbers)1488
Random Number Generation1488
Interrupt1489
Usage Notes1489
Standby Mode1489
Setting the Module Stop Function1489
TSIP-Lite Library1489
Capacitive Touch Sensing Unit (CTSU)1490
Overview1491
Register Descriptions1492
CTSU Control Register 0 (CTSUCR0)1492
CTSU Control Register 1 (CTSUCR1)1494
CTSU Synchronous Noise Reduction Setting Register (CTSUSDPRS)1495
CTSU Sensor Stabilization Wait Control Register (CTSUSST)1496
CTSU Measurement Channel Register 0 (CTSUMCH0)1497
CTSU Measurement Channel Register 1 (CTSUMCH1)1498
CTSU Channel Enable Control Register N (Ctsuchacn) (N = 0 to 3)1499
CTSU Channel Enable Control Register 4 (CTSUCHAC4)1500
CTSU Channel Transmit/Receive Control Register N (Ctsuchtrcn) (N = 0 to 3)1501
CTSU Channel Transmit/Receive Control Register 4 (CTSUCHTRC4)1502
CTSU High-Pass Noise Reduction Control Register (CTSUDCLKC)1503
CTSU Status Register (CTSUST)1504
CTSU High-Pass Noise Reduction Spectrum Diffusion Control Register (CTSUSSC)1506
CTSU Sensor Offset Register 0 (CTSUSO0)1507
CTSU Sensor Offset Register 1 (CTSUSO1)1508
CTSU Sensor Counter (CTSUSC)1509
CTSU Reference Counter (CTSURC)1510
CTSU Error Status Register (CTSUERRS)1511
Operation1513
Principles of Measurement Operation1513
Measurement Modes1515
Initial Setting Flowchart1516
Status Counter1517
Self-Capacitance Single Scan Mode Operation1518
Self-Capacitance Multi-Scan Mode Operation1520
Mutual Capacitance Full Scan Mode Operation1522
Items Common to Multiple Modes1525
Sensor Stabilization Wait Time and Measurement Time1525
Interrupts1526
Usage Notes1528
Measurement Result Data (CTSUSC and CTSURC Counters)1528
Software Trigger1528
External Trigger1528
Notes on Forcibly Stopping Operation1529
TSCAP Pin1529
Notes During Measurement Operation (CTSUCR0.CTSUSTRT Bit = 1)1529
Overview1530
Register Descriptions1535
A/D Data Registers y (Addry) (y = 0 to 7, 16 to 20, 27), A/D Data Duplication Register (ADDBLDR), A/D Temperature Sensor Data Register (ADTSDR), A/D Internal Reference Voltage Data Register (ADOCDR)1535
A/D Self-Diagnosis Data Register (ADRD)1537
A/D Control Register (ADCSR)1538
A/D Channel Select Register A0 (ADANSA0)1541
A/D Channel Select Register A1 (ADANSA1)1542
A/D Channel Select Register B0 (ADANSB0)1543
A/D Channel Select Register B1 (ADANSB1)1544
A/D-Converted Value Addition/Average Function Select Register 0 (ADADS0)1545
A/D-Converted Value Addition/Average Function Select Register 1 (ADADS1)1546
A/D-Converted Value Addition/Average Count Select Register (ADADC)1548
A/D Control Extended Register (ADCER)1549
A/D Conversion Start Trigger Select Register (ADSTRGR)1551
A/D Conversion Extended Input Control Register (ADEXICR)1553
A/D Sampling State Register N (Adsstrn) (N = 0 to 7, L, T, O)1555
A/D Disconnection Detection Control Register (ADDISCR)1556
A/D Event Link Control Register (ADELCCR)1557
A/D Group Scan Priority Control Register (ADGSPCR)1558
A/D Compare Function Control Register (ADCMPCR)1559
A/D Compare Function Window a Channel Select Register 0 (ADCMPANSR0)1561
A/D Compare Function Window a Channel Select Register 1 (ADCMPANSR1)1562
A/D Compare Function Window a Extended Input Select Register (ADCMPANSER)1563
A/D Compare Function Window a Comparison Condition Setting Register 01564
(Adcmplr0)1564
A/D Compare Function Window a Comparison Condition Setting Register 11565
(Adcmplr1)1565
A/D Compare Function Window a Extended Input Comparison Condition Setting Register (ADCMPLER)1566
A/D Compare Function Window a Lower-Side Level Setting Register (ADCMPDR0)1567
A/D Compare Function Window a Upper-Side Level Setting Register (ADCMPDR1)1569
A/D Compare Function Window a Channel Status Register 0 (ADCMPSR0)1570
A/D Compare Function Window a Channel Status Register 1 (ADCMPSR1)1571
A/D Compare Function Window a Extended Input Channel Status Register (ADCMPSER)1572
A/D High-Potential/Low-Potential Reference Voltage Control Register (ADHVREFCNT)1573
A/D Compare Function Window A/B Status Monitor Register (ADWINMON)1574
A/D Compare Function Window B Channel Select Register (ADCMPBNSR)1575
A/D Compare Function Window B Lower-Side Level Setting Register (ADWINLLB)1577
A/D Compare Function Window B Upper-Side Level Setting Register (ADWINULB)1579
A/D Compare Function Window B Channel Status Register (ADCMPBSR)1580
A/D Data Storage Buffer Register N (Adbufn) (N = 0 to 15)1581
A/D Data Storage Buffer Enable Register (ADBUFEN)1582
A/D Data Storage Buffer Pointer Register (ADBUFPTR)1583
Operation1584
Scanning Operation1584
Single Scan Mode1585
Basic Operation1585
Channel Selection and Self-Diagnosis1586
A/D Conversion of Temperature Sensor Output/Internal Reference Voltage1587
A/D Conversion in Double Trigger Mode1588
Continuous Scan Mode1589
Basic Operation1589
Channel Selection and Self-Diagnosis1590
Group Scan Mode1591
Basic Operation1591
A/D Conversion in Double Trigger Mode1592
Operation under Group-A Priority Control1593
Compare Function (Window A, Window B)1602
Compare Function Window A/B1602
ELC Output of Compare Function1604
Using Data Buffers1606
Restrictions for Compare Function1607
Analog Input Sampling Time and Scan Conversion Time1607
Usage Example of A/D Data Register Automatic Clearing Function1609
A/D-Converted Value Addition/Average Mode1609
Disconnection Detection Assist Function1610
Starting A/D Conversion with Asynchronous Trigger1612
Starting A/D Conversion with Synchronous Trigger from Peripheral Module1612
Interrupt Sources and DTC/DMAC Transfer Requests1612
Interrupt Requests1612
Event Link Function1613
Event Output to the ELC1613
12-Bit A/D Converter Operation by Event from the ELC1613
Note on 12-Bit A/D Converter When an Event Is Input from the ELC1613
Selecting Reference Voltage1613
Allowable Impedance of Signal Source1614
Usage Notes1615
Notes on Reading Data Registers1615
Notes on Stopping A/D Conversion1615
A/D Conversion Restarting Timing and Termination Timing1616
Notes on Scan End Interrupt Handling1616
Module Stop Function Setting1616
Notes on Entering Low Power Consumption States1616
Notes on Canceling Software Standby Mode1616
Pin Setting When the 12-Bit A/D Converter Is Used1616
Error in Absolute Accuracy When Disconnection Detection Assistance Is in Use1616
ADHSC Bit Rewriting Procedure1617
Voltage Range of Analog Power Supply Pins1618
Notes on Board Design1619
Notes on Noise Prevention1619
Overview1620
Register Descriptions1621
D/A Data Register M (Dadrm) (M = 0, 1)1621
D/A Control Register (DACR)1622
Data Register Format Select Register (DADPR)1622
D/A A/D Synchronous Start Control Register (DAADSCR)1623
D/A VREF Control Register (DAVREFCR)1624
Operation1625
Measure against Interference between D/A and A/D Conversion1626
Notes on Using the Internal Reference Voltage as the Reference Voltage1628
Event Link Operation Setting Procedure1629
Usage Notes on Event Link Operation1629
Usage Notes1630
Module Stop Function Setting1630
Operation of the D/A Converter in Module Stop State1630
Operation of the D/A Converter in Software Standby Mode1630
Note on Usage When Measure against Interference between D/A and A/D Conversion Is Enabled1630
Temperature Sensor (TEMPSA)1631
Overview1631
Register Descriptions1632
Temperature Sensor Calibration Data Register (TSCDRH, TSCDRL)1632
Using the Temperature Sensor1633
Before Using the Temperature Sensor1633
Setting the 12-Bit A/D Converter1634
Comparator B (Cmpba)1635
Overview1635
Register Descriptions1638
Comparator B1 Control Register 1 (CPB1CNT1)1638
Comparator B1 Control Register 2 (CPB1CNT2)1638
Comparator B1 Flag Register (CPB1FLG)1639
Comparator B1 Interrupt Control Register (CPB1INT)1640
Comparator B1 Filter Select Register (CPB1F)1641
Comparator B1 Mode Select Register (CPB1MD)1641
Comparator B1 Reference Input Voltage Select Register (CPB1REF)1642
Comparator B1 Output Control Register (CPB1OCR)1643
Operation1644
Comparator Bn Digital Filter (N = 2, 3)1648
Comparator Bn Output Function (N = 2, 3)1649
Example of Using Comparator B to Exit Software Standby Mode1649
Comparator B2 and Comparator B3 Interrupts1650
Usage Note1650
Module Stop Function Setting1650
Data Operation Circuit (DOC)1651
Overview1651
Register Descriptions1652
DOC Control Register (DOCR)1652
DOC Data Input Register (DODIR)1653
DOC Data Setting Register (DODSR)1653
Operation1654
Data Comparison Mode1654
Data Addition Mode1655
Data Subtraction Mode1656
Interrupt Requests1656
Event Link Output1657
Interrupt Handling and Event Linking1657
Usage Note1657
Module Stop Function Setting1657
Ram1658
Overview1658
Operation1658
Low Power Consumption Function1658
Notes on Self-Diagnosis of the RAM1658
Flash Memory (FLASH)1659
Overview1659
ROM Area and Block Configuration1660
E2 Dataflash Area and Block Configuration1661
Register Descriptions1662
E2 Dataflash Control Register (DFLCTL)1662
Flash P/E Mode Entry Register (FENTRYR)1663
Protection Unlock Register (FPR)1664
Protection Unlock Status Register (FPSR)1664
Flash P/E Mode Control Register (FPMCR)1665
Flash Initial Setting Register (FISR)1666
Flash Reset Register (FRESETR)1668
Flash Area Select Register (FASR)1668
Flash Control Register (FCR)1669
Flash Extra Area Control Register (FEXCR)1671
Flash Processing Start Address Register H (FSARH)1672
Flash Processing Start Address Register L (FSARL)1672
Flash Processing End Address Register H (FEARH)1673
Flash Processing End Address Register L (FEARL)1673
Flash Write Buffer N Register (Fwbn) (N = 0 to 3)1674
Flash Status Register 0 (FSTATR0)1675
Flash Status Register 1 (FSTATR1)1677
Flash Error Address Monitor Register H (FEAMH)1678
Flash Error Address Monitor Register L (FEAML)1678
Flash Start-Up Setting Monitor Register (FSCMR)1679
Flash Access Window Start Address Monitor Register (FAWSMR)1679
Flash Access Window End Address Monitor Register (FAWEMR)1680
Unique ID Register N (Uidrn) (N = 0 to 3)1680
Start-Up Program Protection1681
Area Protection1682
Programming and Erasure1683
Sequencer Modes1683
E2 Dataflash Access Disabled Mode1683
Read Mode1684
P/E Modes1684
Mode Transitions1684
Transition from E2 Dataflash Access Disable Mode to Read Mode1684
Transition from Read Mode to P/E Mode1685
Transition from P/E Mode to Read Mode1687
Software Commands1689
Software Command Usage1690
Program1690
Block Erase1692
All-Block Erase1694
Blank Check1696
Start-Up Area Information Program/Access Window Information Program1698
Forced Stop of Software Commands1699
Interrupt1699
Boot Mode1700
Boot Mode (USB Interface)1701
Operating Conditions in Boot Mode (USB Interface)1701
Boot Mode (SCI Interface)1704
Operating Conditions in Boot Mode (SCI Interface)1704
Starting up in Boot Mode (SCI Interface)1705
Boot Mode (FINE Interface)1706
Operating Conditions in Boot Mode (FINE Interface)1706
Flash Memory Protection1707
ID Code Protection1707
Boot Mode ID Code Protection1708
On-Chip Debugging Emulator ID Code Protection1709
ROM Code Protection1710
Communication Protocol1711
State Transition in Boot Mode (SCI Interface)1711
Command and Response Configuration1712
Response to Undefined Commands1712
Boot Mode Status Inquiry1713
Inquiry Commands1714
Supported Device Inquiry1714
Data Area Availability Inquiry1715
User Area Information Inquiry1715
Data Area Information Inquiry1716
Block Information Inquiry1716
Setting Commands1717
Device Select1717
Operating Frequency Select1718
Program/Erase Host Command Wait State Transition1719
ID Code Authentication Command1720
ID Code Check1720
Program/Erase Commands1721
User/Data Area Program Preparation1721
Program1722
Data Area Program1723
Erase Preparation1724
Block Erase1724
Read-Check Commands1725
Memory Read1725
User Area Checksum1726
Data Area Checksum1727
User Area Blank Check1727
Data Area Blank Check1728
Access Window Information Program1728
Access Window Read1729
Serial Programmer Operation in Boot Mode (SCI Interface)1730
Bit Rate Automatic Adjustment Procedure1731
Procedure to Receive the MCU Information1732
Procedure to Select the Device and Change the Bit Rate1733
Procedure for Transition to the Program/Erase Host Command Wait State1734
Procedure to Unlock Boot Mode ID Code Protection1735
Procedure to Erase the User Area and Data Area1736
Procedure to Program the User Area and Data Area1737
Procedure to Check Data in the User Area1738
Procedure to Check Data in the Data Area1739
Procedure to Set the Access Window in the User Area1740
50.12 Rewriting by Self-Programming1741
Overview1741
Usage Notes1742
50.14 Usage Notes in Boot Mode1743
Electrical Characteristics1744
Absolute Maximum Ratings1744
DC Characteristics1746
Normal I/O Pin Output Characteristics (1)1761
Normal I/O Pin Output Characteristics (2)1763
Normal I/O Pin Output Characteristics (3)1765
AC Characteristics1767
Clock Timing1767
Reset Timing1772
Timing of Recovery from Low Power Consumption Modes1774
Control Signal Timing1777
Timing of On-Chip Peripheral Modules1778
USB Characteristics1792
A/D Conversion Characteristics1794
D/A Conversion Characteristics1801
Temperature Sensor Characteristics1803
Comparator Characteristics1803
CTSU Characteristics1805
51.10 Characteristics of Power-On Reset Circuit and Voltage Detection Circuit1805
51.11 Oscillation Stop Detection Timing1808
51.12 Battery Backup Function Characteristics1809
51.13 ROM (Flash Memory for Code Storage) Characteristics1810
E2 Dataflash Characteristics (Flash Memory for Data Storage)1812
BLE Characteristics1813
Transmission Characteristics1813
Reception Characteristics (2 Mbps)1813
Reception Characteristics (1 Mbps)1814
Reception Characteristics (500 Kbps)1814
Reception Characteristics (125 Kbps)1815
Usage Notes1816
Connecting VCL Capacitor and Bypass Capacitors1816
Appendix 1. Port States in each Processing Mode1817
Appendix 2. Package Dimensions1818
Revision History1820

Renesas RX Series

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