Renesas RX Series User Manual

R01UH0823EJ0100 Rev.1.00 Page 659 of 1823
Jul 31, 2019
RX23W Group 25. 16-Bit Timer Pulse Unit (TPUa)
Figure 25.1 Block Diagram of TPU
Internal peripheral bus
A/D conversion start
request signal
TPU3
TMDR
TIORL
TCR
TIORH
TGRA
TCNT
TGRB
TGRC TGRD
TPU4
TMDR
TSR
TCR
TIOR
TIER
TGRA
TCNT
TGRB
TPU5
TMDR
TCR
TIOR
TGRA
TCNT
TGRB
Control logic for TPU3 to TPU5
TPU2
TMDR
TSR
TCR
TIOR
TIER
TGRA
TCNT
TGRB
TGRC
TPU1
TMDRTCR
TIOR
TGRA
TCNT
TGRB
TPU0
Control logic for TPU0 to TPU2
TGRA
TCNT
TGRB
TGRD
TSYRTSTR
Module data bus
Bus interface
Common
Control
logic
[Input/output pins]
TIOCA3
TIOCB3
TIOCC3
TIOCD3
TIOCA4
TIOCB4
TIOCB5
TPU3:
TPU4:
TPU5:
PCLK/1
PCLK/4
PCLK/16
PCLK/64
PCLK/256
PCLK/1024
PCLK/4096
TCLKA
TCLKB
TCLKC
TCLKD
[Clock input]
Internal clock:
External clock:
TIOCB0
TIOCB1
TIOCB2
TPU0:
TPU1:
TPU2:
[Input/output pins]
[Interrupt request signals]
TPU3:
TPU4:
TPU5:
TGI3A
TGI3B
TGI3C
TGI3D
TCI3V
TGI4A
TGI4B
TCI4V
TCI4U
TGI5A
TGI5B
TCI5V
TCI5U
[Interrupt request signals]
TGI0A
TGI0B
TGI0C
TGI0D
TCI0V
TGI1A
TGI1B
TCI1V
TCI1U
TGI2A
TGI2B
TCI2V
TCI2U
TPU0:
TPU1:
TPU2:
TSRTIER
NFCR
NFCR
TSRTIER
NFCR
NFCR
NFCR
TMDR
TIORL
TCR
TIORH
TSR
TIER
NFCR
TIER TSR
TSTR: Timer start register
TSYR: Timer synchronous register
TCR: Timer control register
TMDR: Timer mode register
TIOR (H, L): Timer I/O control registers (H, L)
TIER: Timer interrupt enable register
TSR: Timer status register
TGR (A, B, C, D): Timer general registers (A, B, C, D)
TCNT: Timer counter
NFCR: Noise filter control register

Renesas RX Series Specifications

General

Brand	Renesas
Model	RX Series
Category	Microcontrollers
Language	English