Renesas RX Series User Manual

R01UH0823EJ0100 Rev.1.00 Page 711 of 1823
Jul 31, 2019
RX23W Group 25. 16-Bit Timer Pulse Unit (TPUa)
(2) Output Compare Output Timing
A compare match signal is generated in the final state in which TPUm.TCNT and TPUm.TGRy match (the point at
which the count value matched by TCNT is updated). When a compare match signal is generated, the output value set in
TPUm.TIORH, TPUm.TIORL, or TPUm.TIOR is output to the output compare output pin TIOCyn (y = A to D; n = 0 to
5). After a match between TCNT and TGRy, the compare match signal is not generated until the TCNT input clock is
generated.
Figure 25.33 shows output compare output timing.
Figure 25.33 Output Compare Output Timing
(3) Input Capture Signal Timing
Figure 25.34 shows input capture signal timing.
Figure 25.34 Input Capture Signal Timing
N
TCNT input clock
Compare match signal
TPUm.TCNT
TPUm.TGRy
PCLK
N + 1
TIOCyn pin
N
N N + 1 N + 2
N N + 2
Input capture
input
Input capture
signal
TPUm.TCNT
TPUm.TGRy
PCLK

Renesas RX Series Specifications

General

Brand	Renesas
Model	RX Series
Category	Microcontrollers
Language	English