R01UH0823EJ0100 Rev.1.00 Page 824 of 1823
Jul 31, 2019
RX23W Group 30. Watchdog Timer (WDTA)
Table 30.3 lists the counter values for the window start and end positions and Figure 30.2 shows the refresh-permitted
period set by the RPSS[1:0], RPES[1:0], and TOPS[1:0] bits.
Figure 30.2 RPSS[1:0] and RPES[1:0] Bit Settings and the Refresh-Permitted Period
Table 30.3 Relationship between Timeout Period and Window Start and End Counter Values
TOPS[1:0] Bits
Timeout Period Window Start and End Counter Value
Cycles Counter Value 100% 75% 50% 25%
0 0 1024 03FFh 03FFh 02FFh 01FFh 00FFh
0 1 4096 0FFFh 0FFFh 0BFFh 07FFh 03FFh
1 0 8192 1FFFh 1FFFh 17FFh 0FFFh 07FFh
1 1 16384 3FFFh 3FFFh 2FFFh 1FFFh 0FFFh
Window
Start
(%)
End
1
25
Note: If window end setting  window start setting, the window end setting
is set to 0%.
0%
Refresh-permitted period
Underflow
100% 75% 50% 25%
100
75
50
Counting
started
RPSS[1:0] Bits
RPES[1:0] Bits
1
Refresh-prohibited period
(%)
1
1
10
0
0
0
1
1
10
0
0
0
1
1
1
10
0
0
0
1
1
1
10
0
0
0
1
1
1
10
0
0
0
0
25
50
75
0
25
50
75
0
25
50
75
0
25
50
75
b13
b9
b12
b8