Renesas RX Series User Manual

R01UH0823EJ0100 Rev.1.00 Page 993 of 1823
Jul 31, 2019
RX23W Group 33. Serial Communications Interface (SCIg, SCIh)
Table 33.18 BRR Settings for Various Bit Rates (Clock Synchronous Mode, Simple SPI Mode)
Blank cell: Cannot be set since the bit rate error exceeds 5%.
—: Can be set, but a bit rate error of 1 to 5% will occur.
Note 1. Continuous transmission or reception is not possible. After transmitting/receiving one frame of data, there is an interval of a 1-bit
period before starting transmitting/receiving the next frame of data. The output of the synchronization clock is stopped for a 1-bit
period. For this reason, it takes 9 bits worth of time to transfer one frame (8 bits) of data, and the average transfer rate is 8/9
times the bit rate.
Bit Rate (bps)
Operating Frequency PCLK (MHz)
8 1016202530
nNnNnNnNnNnN
110
250 3 124 3 155 3 249
500 2 249 3 77 3 124 3 155 3 194 3 233
1 k 2 124 2 155 2 249 3 77 3 97 3 116
2.5 k 1 199 1 249 2 99 2 124 2 155 2 187
5 k 1 99 1 124 1 199 1 249 2 77 2 93
10 k 0 199 0 249 1 99 1 124 1 155 1 187
25 k 079099015901990249174
50 k 03904907909901240149
100 k 019024039049062074
250 k 0709015019024029
500 k 03040709——014
1 M 01 0304——
2 M 0 0*
1
01 ——
2.5 M 0 0*
1
01 02
4 M 0 0*
1
5 M 00*
1
6.25 M 00*
1
7.5 M 00*
1
Table 33.19 Maximum Bit Rate with External Clock Input (Clock Synchronous Mode, Simple SPI Mode)
PCLK (MHz) External Input Clock (MHz) Maximum Bit Rate (Mbps)
8 1.3333 1.3333
10 1.6667 1.6667
12 2.0000 2.0000
14 2.3333 2.3333
16 2.6667 2.6667
18 3.0000 3.0000
20 3.3333 3.3333
25 4.1667 4.1667
30 5.0000 5.0000

Renesas RX Series Specifications

General

Brand	Renesas
Model	RX Series
Category	Microcontrollers
Language	English