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I2C Registers
227
SWRU543–January 2019
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Inter-Integrated Circuit (I
2
C) Interface
Table 7-6. Write Field Decoding for I2CMCS[6:0] (continued)
Current
State
I2CMSA[
0]
I2CMCS[6:0]
Next State Description
R/S BURST QCCMD HS ACK STOP START RUN
Master
Transmit
X 0 0 0 X 0 0 1
TRANSMIT operation (master remains in Master
Transmit state).
X 0 0 0 X 1 0 0 STOP condition (master goes to Idle state).
X 0 0 0 X 1 0 1
TRANSMIT followed by STOP condition (master goes
to Idle state).
X 1 0 0 X 0 0 0
N FIFO-serviced TRANSMIT operations (master
remains in Master Transmit state).
X 1 0 0 X 1 0 0
N FIFO-serviced TRANSMIT operations followed by
STOP condition (master goes to Idle state).
0 0 0 0 X 0 1 1
Repeated START condition followed by a TRANSMIT
operation (master remains in Master Transmit state).
0 0 0 0 X 1 1 1
Repeated START condition followed by TRANSMIT
and STOP condition (master goes to Idle state).
0 1 0 0 X 0 1 0
Repeated START condition followed by N FIFO-
serviced TRANSMIT operations (master remains in
Master Transmit state).
0 1 0 0 X 1 1 0
Repeated START condition followed by N FIFO-
serviced TRANSMIT operations and STOP condition
(master goes to Idle state).
1 0 0 0 0 0 1 1
Repeated START condition followed by a RECEIVE
operation with a negative ACK (master goes to Master
Receive state).
1 0 0 0 0 1 1 1
Repeated START condition followed by a RECEIVE
and STOP condition (master goes to Idle state).
1 0 0 0 1 0 1 1
Repeated START condition followed by RECEIVE
operation (master goes to Master Receive state).
1 1 0 0 0 0 1 0
Repeated START condition followed by N FIFO-
serviced RECEIVE operations with a negative ACK on
the last RECEIVE operation (master goes to Master
Receive state).
1 1 0 0 0 1 1 0
Repeated START condition followed by N FIFO-
serviced RECEIVE operations and STOP condition
(master goes to Idle state).
1 1 0 0 1 0 1 0
Repeated START condition followed by N FIFO-
serviced RECEIVE operations (master goes to Master
Receive state).
1 0 0 0 1 1 1 1 Illegal
1 1 0 0 1 1 1 0 Illegal