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I2S Registers
439
SWRU543–January 2019
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Inter-Integrated Sound (I2S) Multichannel Audio Serial Port
Table 12-21. XGBLCTL Register Field Descriptions (continued)
Bit Field Type Reset Description
3 RSMRST R 0h
Receive state machine reset enable bit. A read of this bit returns the
RSMRST bit value of GBLCTL. Writes have no effect.
2 RSRCLR R 0h
Receive serializer clear enable bit. A read of this bit returns the
RSRSCLR bit value of GBLCTL. Writes have no effect.
1 RHCLKRST R 0h
Receive high-frequency clock divider reset enable bit. A read of this
bit returns the RHCLKRST bit value of GBLCTL. Writes have no
effect.
0 RCLKRST R 0h
Receive clock divider reset enable bit. A read of this bit returns the
RCLKRST bit value of GBLCTL. Writes have no effect.
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