www.ti.com
DMA_RIS Register (offset = A4h) [reset = 0h]
797
SWRU543–January 2019
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
CC3235x Device Miscellaneous Registers
Table B-7. DMA_RIS Register Field Descriptions (continued)
Bit Field Type Reset Description
0 SDIOMRD R/W 0h
SDIOM_RD_DMA_DONE_INT_STS_RAW
0h = Corresponding interrupt is inactive.
1h = Corresponding interrupt is active. Read is non-destructive.
To Next Page
Loading...
